95 packaging design engineer jobs at 49 companies in Hercules, CA
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Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
3mo
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Senior, Packaging Design Engineer
Sunnyvale, California, United States
$163k-$199k/yr OnsiteFull Time
8+ YOE8+ years in medical device packaging design; BS in Packaging/Mechanical/Industrial Engineering; experience with thermoforming, pouch sealing, ISO11607, CFR 820; CAD (SolidWorks); travel; strong communication.
SolidWorks, FEA, Packaging testing tools, MS Office
1mo
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Advanced Packaging Design Engineer
Santa Clara or Chandler
$192k-$287k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in engineering,5-10 years advanced packaging design experience, expertise with Cadence APD, high-speed interfaces, substrate and assembly processes, and cross-functional collaboration.
Cadence APD, AutoCAD
1w
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Packaging Design Engineer, Platforms Infrastructure Engineering
Sunnyvale, California, United States
$159k-$230k/yr OnsiteFull Time
5+ YOEBachelor's degree or equivalent practical experience, 5+ years in hardware or consumer-goods packaging design, ISTA and ASTM D4169 experience, and CAD proficiency. CPP, master's degree, and 8 years' experience preferred.
ISTA, ASTM D4169, computer-aided design (CAD), Creo, NX, SolidWorks, TOPS, CAPE, FEA
2w
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Senior Packaging Engineer
Palo Alto, California, United States
$211k-$224k/yr OnsiteFull Time
5+ YOERequires 5+ years in packaging, mechanical design, or industrial design; advanced packaging and structural mechanics knowledge; CAD and palletization software expertise; testing, documentation, collaboration, and travel ability.
ArtiosCAD, Esko, SolidWorks, CATIA, CAPE, TOPS, CAD
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Experience in packaging engineering including supplier management, test plan development and lab testing, Design for Transportability (DFT), packaging standards, continuous improvement, and ability to lead projects.
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Packaging engineering experience with supplier management, test plan development, Design For Transportability (DFT), standards development, continuous improvement, and ability to train others; travel ~10%.
2mo
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Manufacturing Design Engineer (MDE) - Packaging
Cupertino, California, United States
OnsiteFull Time
Managing R&D, selection, and implementation of manufacturing processes for consumer packaging parts and assemblies; strong product and process engineering skills.
6d
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Senior Packaging Engineer
Reno or San Francisco or California or Singapore
$130k-$200k/yr OnsiteFull Time
3+ YOEBachelor's degree in mechanical engineering or related field, or equivalent experience; 3+ years designing component packaging from concept to production; expertise in CAD, CAE simulation, GD&T, tolerance analysis, and DFM/DFA.
CATIA, Solidworks, Ansys, Jira, Scrum, 3D EXPERIENCE, FEA
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Advanced Packaging Engineer
Mountain View, California, United States
$200k-$350k/yr OnsiteFull Time
10+ YOE10+ years in advanced multi-die packaging (SiP, CoWoS, EMIB, interposers); expertise in design layout, SI/PI, thermo-mechanical tradeoffs; hands-on with packaging flows for 2.5D/3D; ability to collaborate with architects; DFT/RTL/PD optional.
2mo
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Principal Packaging Engineer
Palo Alto or United States or Canada
$180k-$240k/yr HybridFull Time
B.S./M.S. in EE or related, expertise in multi-die package design and UCIe, substrate and SI/PI knowledge, experience with TSMC/OSAT and managing subcontractors; HFSS/Sigrity familiarity a plus.
HFSS, Sigrity, UCIe
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Principal Packaging Engineer, Optical Interfaces
Santa Clara, California, United States
$145k-$255k/yr OnsiteFull Time
10+ YOE10+ years packaging design experience for optical/photonic components, experience with PIC edge coupling, reliability engineering, CAD and FEA usage, and working with contract manufacturers.
CAD, FEA
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Senior IC Packaging Development Engineer
Santa Clara, California, United States
$168k-$345k/yr OnsiteFull Time
12+ YOERequires a BS, MS, PhD, or equivalent in materials science, engineering, physics, or a related semiconductor field, plus 12+ years of IC packaging development or package design experience.
Cadence Allegro Package Designer, ANSYS, ABAQUS, SEM, EDX, CSAM, X-Ray, LIT
2mo
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Sr Principal Laser Packaging Engineer
Fremont, California, United States
$200k-$280k/yr OnsiteFull Time
10+ YOEPhD in a related field, 10+ years R&D experience in optoelectronic package design transferred to manufacturing, submicron optical alignment, FEA/thermal design, GR-468 qualification, NPI, and strong supplier/customer communication.
Finite Element Analysis (FEA), CFD
1mo
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Package Design Methodology Engineer
Santa Clara or Austin or California
$136k-$265k/yr HybridFull Time
5+ YOEBS or equivalent and 5+ years developing package design flows; strong Python/C++ skills; experience applying AI/ML and LLMs in engineering workflows; solid VLSI package design fundamentals.
Python, C++, LLMs, EDA, AI/ML
3w
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Package Design & Layout Engineer
Palo Alto, California, United States
OnsiteFull Time
6+ YOE6+ years IC package physical design experience, BS/MS in electrical engineering, expertise in package layout tools, multi-die packaging, substrate stack-ups, DFM/DF A closure, and English fluency.
Cadence Allegro Package Designer, APD+, Siemens Xpedition Package Designer, Synopsys IC Package, SKILL, Python, Cadence Sigrity, PowerSI, Ansys, Virtuoso, KLayout, AutoCAD, Cadence Integrity 3D-IC
1mo
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Package Design Methodology Engineer
Santa Clara or Austin or United States
$136k-$265k/yr HybridFull Time
5+ YOEBS in CS/EE or equivalent,5+ years developing package design flows/methodologies,proficiency in Python and/or C++,knowledge of VLSI package electrical fundamentals,experience applying AI/ML or LLMs in engineering workflows.
Python, C++, LLMs, EDA
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PCB Design Engineer
San Francisco or Austin or Boston
HybridFull Time
Experience designing, validating, and bringing up high-power-density, high-layer-count, large-format PCBs, with knowledge of chip-package interactions and design for manufacturing.
1mo
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Package Design Engineer - Staff
Santa Clara or San Diego
$154k-$253k/yr OnsiteFull Time
5+ YOEExperience in IC package/SIP physical design, Cadence APD/Allegro proficiency, familiarity with SI/PI tools (HFSS, PowerSI, Q3D), package verification and CAD tool development; master\u0002s preferred with 5+ years.
Cadence APD, Cadence Allegro, PCB Editor, Advanced Package Designer, APD/SiP, XtractIM, PowerSI, HFSS, Q3D, Calibre
2mo
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Sr. Engineer, Package Design
Santa Clara, California, United States
$139k-$191k/yr OnsiteFull Time
5+ YOEM.S. or PhD in Mechanical Engineering/Materials Science or related field; 5+ years semiconductor IC packaging experience; experience with OSATs, flip-chip/leadframe/substrate packages, thermal/stress/electrical modeling; AutoCAD experience.
AutoCAD