78 packaging design engineer jobs at 31 companies in Hollister, CA
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Packaging Design Engineer
San Jose or San Diego
HybridFull Time
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
Cadence, SKILL, Ansys, AutoCAD
3mo
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Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
3mo
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Senior, Packaging Design Engineer
Sunnyvale, California, United States
$163k-$199k/yr OnsiteFull Time
8+ YOE8+ years in medical device packaging design; BS in Packaging/Mechanical/Industrial Engineering; experience with thermoforming, pouch sealing, ISO11607, CFR 820; CAD (SolidWorks); travel; strong communication.
SolidWorks, FEA, Packaging testing tools, MS Office
1mo
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Advanced Packaging Design Engineer
Santa Clara or Chandler
$192k-$287k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in engineering,5-10 years advanced packaging design experience, expertise with Cadence APD, high-speed interfaces, substrate and assembly processes, and cross-functional collaboration.
Cadence APD, AutoCAD
1w
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Packaging Design Engineer, Platforms Infrastructure Engineering
Sunnyvale, California, United States
$159k-$230k/yr OnsiteFull Time
5+ YOEBachelor's degree or equivalent practical experience, 5+ years in hardware or consumer-goods packaging design, ISTA and ASTM D4169 experience, and CAD proficiency. CPP, master's degree, and 8 years' experience preferred.
ISTA, ASTM D4169, computer-aided design (CAD), Creo, NX, SolidWorks, TOPS, CAPE, FEA
2mo
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Experience in packaging engineering including supplier management, test plan development and lab testing, Design for Transportability (DFT), packaging standards, continuous improvement, and ability to lead projects.
2mo
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Packaging engineering experience with supplier management, test plan development, Design For Transportability (DFT), standards development, continuous improvement, and ability to train others; travel ~10%.
2mo
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Manufacturing Design Engineer (MDE) - Packaging
Cupertino, California, United States
OnsiteFull Time
Managing R&D, selection, and implementation of manufacturing processes for consumer packaging parts and assemblies; strong product and process engineering skills.
1w
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Packaging Tech Lead Design Engineer
San Jose, California, United States
$185k-$240k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical or computer engineering and 5+ years of digital design experience, including a full chip from specification to tapeout. Requires Verilog/SystemVerilog, RTL, synthesis, timing closure, CDC, lint, and low-power expertise.
Verilog, SystemVerilog, RTL, CDC, DFT, BIST, PCIe, CXL, Ethernet, NVLink, UALink, UCIe, COSMOS, SoC
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Principal Packaging Engineer, Optical Interfaces
Santa Clara, California, United States
$145k-$255k/yr OnsiteFull Time
10+ YOE10+ years packaging design experience for optical/photonic components, experience with PIC edge coupling, reliability engineering, CAD and FEA usage, and working with contract manufacturers.
CAD, FEA
2mo
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Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
2w
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Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
1mo
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Senior IC Packaging Development Engineer
Santa Clara, California, United States
$168k-$345k/yr OnsiteFull Time
12+ YOERequires a BS, MS, PhD, or equivalent in materials science, engineering, physics, or a related semiconductor field, plus 12+ years of IC packaging development or package design experience.
Cadence Allegro Package Designer, ANSYS, ABAQUS, SEM, EDX, CSAM, X-Ray, LIT
1mo
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Package Design Methodology Engineer
Santa Clara or Austin or California
$136k-$265k/yr HybridFull Time
5+ YOEBS or equivalent and 5+ years developing package design flows; strong Python/C++ skills; experience applying AI/ML and LLMs in engineering workflows; solid VLSI package design fundamentals.
Python, C++, LLMs, EDA, AI/ML
4w
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Package Design Engineer
San Jose or Austin or Fort Collins
$122k-$195k/yr OnsiteFull Time
6+ YOEBSEE with 8+ years or MSEE with 6+ years in flip-chip BGA package design; knowledge of package signal and power integrity; Cadence APD and Cadence SKILL experience preferred; project management and collaboration skills.
Cadence APD, Cadence SKILL
1mo
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Package Design Methodology Engineer
Santa Clara or Austin or United States
$136k-$265k/yr HybridFull Time
5+ YOEBS in CS/EE or equivalent,5+ years developing package design flows/methodologies,proficiency in Python and/or C++,knowledge of VLSI package electrical fundamentals,experience applying AI/ML or LLMs in engineering workflows.
Python, C++, LLMs, EDA
1mo
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IC Package Design Engineer
San Jose, California, United States
$153k-$219k/yr HybridFull Time
3+ YOEBachelor's (5+ years) or Master’s (3+ years) in Electrical Engineering or related field; experience in package/PCB/high-speed design, power delivery, and EDA tools; scripting (Python, Perl, TCL, shell) and strong collaboration skills.
EDA, Python, Perl, TCL, Shell
3mo
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Advanced Packaging SI/PI Engineer
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
8+ YOEBachelor's or Master's in Electrical/Computer Engineering; 8+ years SI/PI experience on high-performance ASIC/accelerator platforms; PDN design, high-speed interfaces; proficiency with SI/PI tools; packaging/OSAT/ODM collaboration.
ANSYS HFSS, SIwave, Cadence Sigrity, Keysight ADS
1mo
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Package Design Engineer - Staff
Santa Clara or San Diego
$154k-$253k/yr OnsiteFull Time
5+ YOEExperience in IC package/SIP physical design, Cadence APD/Allegro proficiency, familiarity with SI/PI tools (HFSS, PowerSI, Q3D), package verification and CAD tool development; master\u0002s preferred with 5+ years.
Cadence APD, Cadence Allegro, PCB Editor, Advanced Package Designer, APD/SiP, XtractIM, PowerSI, HFSS, Q3D, Calibre
1mo
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Principal Package Design Engineer
San Jose, California, United States
$195k-$240k/yr HybridFull Time
5+ YOEMSc/PhD in engineering, 5+ years semiconductor packaging experience, expertise in advanced packaging architectures, reliability testing, thermal/mechanical/electrical analysis, OSAT collaboration, and project leadership.
Cadence Allegro Package Designer, Solid works, ANSYS, COMSOL, JMP, Minitab