53 packaging designer jobs at 23 companies in Lathrop, CA
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Experience in packaging engineering including supplier management, test plan development and lab testing, Design for Transportability (DFT), packaging standards, continuous improvement, and ability to lead projects.
2mo
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Sr Packaging Engineer
Santa Clara, California, United States
$134k-$184k/yr OnsiteFull Time
Packaging engineering experience with supplier management, test plan development, Design For Transportability (DFT), standards development, continuous improvement, and ability to train others; travel ~10%.
3mo
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Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
TransPak: Packaging solutions provider
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
1mo
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Principal Packaging Engineer, Optical Interfaces
Santa Clara, California, United States
$145k-$255k/yr OnsiteFull Time
10+ YOE10+ years packaging design experience for optical/photonic components, experience with PIC edge coupling, reliability engineering, CAD and FEA usage, and working with contract manufacturers.
CAD, FEA
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Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
3mo
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Photonic Packaging Engineer, Principal
San Jose, California, United States
OnsiteFull Time
10+ YOEPh.D. or M.S. in EE, Physics, Materials Science, Mechanical Engineering, or related field; 10+ years in photonic packaging or related areas; strong expertise in high-speed packaging, thermal management, and optomechanical design.
1mo
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Advanced Packaging Design Engineer
Santa Clara or Chandler
$192k-$287k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in engineering,5-10 years advanced packaging design experience, expertise with Cadence APD, high-speed interfaces, substrate and assembly processes, and cross-functional collaboration.
Cadence APD, AutoCAD
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Sr Principal Laser Packaging Engineer
Fremont, California, United States
$200k-$280k/yr OnsiteFull Time
10+ YOEPhD in a related field, 10+ years R&D experience in optoelectronic package design transferred to manufacturing, submicron optical alignment, FEA/thermal design, GR-468 qualification, NPI, and strong supplier/customer communication.
Finite Element Analysis (FEA), CFD
2mo
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Senior Power Integrity Engineer - LPU Packaging
Santa Clara, California, United States
$196k-$368k/yr OnsiteFull Time
12+ YOEMS/PhD or equivalent, 12+ years in power integrity for high-current, low-voltage rails; chip-package-board PDN design and sign-off; experience with advanced packages (FCBGA, 25D/3D, HBM); PDN simulation and lab validation using industry tools.
PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, SPICE, S-parameter, IBIS-AMI, VNA, oscilloscope, PDN analyzer
2mo
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
2mo
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Senior Signal Integrity Engineer – LPU Packaging
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
8+ YOEBS/MS/PhD in EE or equivalent, 8+ years in signal integrity/high-speed interconnects, SerDes/channel design, electromagnetics, simulation-to-measurement correlation using VNA/TDR/scope, and experience with industry SI tools.
Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, IBIS-AMI, S-parameters, VNA, TDR, oscilloscope
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Staff Software Engineer, Pricing and Packaging Engineering
San Francisco or Denver or New York City or San Jose
$197k-$247k/yr HybridFull Time
8+ YOE8+ years building large-scale backend platform systems (commerce/billing/subscriptions preferred); strong distributed systems, API design, SLO, and mentorship experience; proven delivery of multi-quarter projects.
1mo
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ASIC Package Design Manager
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOE3+ MgmtManage and develop engineers for flip-chip-BGA package designs; requires 12+ years package design experience, 3+ years management, Ohio? (not stated), knowledge of SI/PI, project management and cross-functional collaboration.
1mo
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Package Design Engineer - Staff
Santa Clara or San Diego
$154k-$253k/yr OnsiteFull Time
5+ YOEExperience in IC package/SIP physical design, Cadence APD/Allegro proficiency, familiarity with SI/PI tools (HFSS, PowerSI, Q3D), package verification and CAD tool development; master\u0002s preferred with 5+ years.
Cadence APD, Cadence Allegro, PCB Editor, Advanced Package Designer, APD/SiP, XtractIM, PowerSI, HFSS, Q3D, Calibre
1d
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2027 Undergrad ASIC Package Engineering Co-op/Intern
San Jose or Santa Clara
$64k-$96k/yr HybridInternship, Temporary
Current U.S. university bachelor's student in engineering or a related field; knowledge of circuits, package/PCB design, Perl, Python, SQL, semiconductor packaging, or Power BI encouraged.
Perl, Python, SQL, Power BI
2w
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3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
4+ YOEMSEE/BSEE and 4+ years of design experience with advanced IC package or interposer layout. Requires package design tools, scripting, Windows/Linux, and strong presentation and customer skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux
1mo
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Principal Package Design Engineer
San Jose, California, United States
$195k-$240k/yr HybridFull Time
5+ YOEMSc/PhD in engineering, 5+ years semiconductor packaging experience, expertise in advanced packaging architectures, reliability testing, thermal/mechanical/electrical analysis, OSAT collaboration, and project leadership.
Cadence Allegro Package Designer, Solid works, ANSYS, COMSOL, JMP, Minitab
2mo
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SPE Signal Integrity Engineer
Johns Creek or San Jose or Bangalore or Seoul
$134k-$249k/yr OnsiteFull Time
10+ YOESenior-level SI/PI engineer with 10+ years in DDR4/5, EM theory, and package design.
ADS, HFSS, Q3D/PowerSI, Spice
3mo
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Senior Technical Program Manager (Silicon)
San Jose, California, United States
OnsiteFull Time
10+ YOE10+ years in silicon design/tapeout, packaging, bring-up, validation; BS in EE/CE; strong PM skills.
MS Project, Jira, Asana, Smartsheet
1mo
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Staff Mechanical Engineer
Fremont or Salem
$185k-$240k/yr HybridFull Time
8+ YOE8+ years mechanical design experience, B.S./M.S. in Mechanical Engineering, experience with mechanism design, electronics packaging, FEA/thermal analysis, Creo, Windchill, Jira/Confluence; ability to mentor engineers.
Creo, Windchill, Jira, Confluence
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