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26 packaging designer jobs at 17 companies in Manteca, CA

1mo
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Category Graphic Designer - Contractor
Atlanta or Walnut Creek
HybridContract
Central Garden & Pet
Central Garden & PetNASDAQ: CENT: Manufacturer and distributor of lawn, garden, and pet products.
3+ YOE3+ years packaging/graphic design experience in CPG or retail, strong stakeholder partnership and project management, proficiency in Adobe Creative Suite and Wrike, bachelor's degree or equivalent, portfolio required.
Adobe Creative Suite, Wrike
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3mo
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Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
TransPak: Packaging solutions provider
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
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1mo
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Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
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2mo
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Photonic Packaging Engineer, Principal
San Jose, California, United States
OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
10+ YOEPh.D. or M.S. in EE, Physics, Materials Science, Mechanical Engineering, or related field; 10+ years in photonic packaging or related areas; strong expertise in high-speed packaging, thermal management, and optomechanical design.
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2mo
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Sr Principal Laser Packaging Engineer
Fremont, California, United States
$200k-$280k/yr OnsiteFull Time
Koch Inc.
Koch Inc.: Operates global manufacturing, refining, and industrial technology businesses.
10+ YOEPhD in a related field, 10+ years R&D experience in optoelectronic package design transferred to manufacturing, submicron optical alignment, FEA/thermal design, GR-468 qualification, NPI, and strong supplier/customer communication.
Finite Element Analysis (FEA), CFD
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
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Staff Software Engineer, Pricing and Packaging Engineering
San Francisco or Denver or New York City or San Jose
$197k-$247k/yr HybridFull Time
Gusto
Gusto: Cloud-based payroll and HR software for small businesses.
8+ YOE8+ years building large-scale backend platform systems (commerce/billing/subscriptions preferred); strong distributed systems, API design, SLO, and mentorship experience; proven delivery of multi-quarter projects.
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ASIC Package Design Manager
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOE3+ MgmtManage and develop engineers for flip-chip-BGA package designs; requires 12+ years package design experience, 3+ years management, Ohio? (not stated), knowledge of SI/PI, project management and cross-functional collaboration.
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5d
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3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
Siemens
SiemensXETRA: SIE: Manufactures industrial automation, infrastructure, and energy technology systems.
4+ YOEMSEE/BSEE and 4+ years of design experience with advanced IC package or interposer layout. Requires package design tools, scripting, Windows/Linux, and strong presentation and customer skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux
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2w
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Principal Package Design Engineer
San Jose, California, United States
$195k-$240k/yr HybridFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
5+ YOEMSc/PhD in engineering, 5+ years semiconductor packaging experience, expertise in advanced packaging architectures, reliability testing, thermal/mechanical/electrical analysis, OSAT collaboration, and project leadership.
Cadence Allegro Package Designer, Solid works, ANSYS, COMSOL, JMP, Minitab
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2mo
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SPE Signal Integrity Engineer
Johns Creek or San Jose or Bangalore or Seoul
$134k-$249k/yr OnsiteFull Time
Rambus
RambusNASDAQ: RMBS: Develops high-performance memory interface chips and semiconductor IP.
10+ YOESenior-level SI/PI engineer with 10+ years in DDR4/5, EM theory, and package design.
ADS, HFSS, Q3D/PowerSI, Spice
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3mo
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Senior Technical Program Manager (Silicon)
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
10+ YOE10+ years in silicon design/tapeout, packaging, bring-up, validation; BS in EE/CE; strong PM skills.
MS Project, Jira, Asana, Smartsheet
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1mo
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Staff Mechanical Engineer
Fremont or Salem
$185k-$240k/yr HybridFull Time
Agility Robotics
Agility Robotics: Develops bipedal humanoid robots for industrial warehouse automation.
8+ YOE8+ years mechanical design experience, B.S./M.S. in Mechanical Engineering, experience with mechanism design, electronics packaging, FEA/thermal analysis, Creo, Windchill, Jira/Confluence; ability to mentor engineers.
Creo, Windchill, Jira, Confluence
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3w
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Signal and Power Integrity Senior Application Engineer
San Jose, California, United States
$84k-$156k/yr OnsiteFull Time
Cadence Design Systems
Cadence Design SystemsNASDAQ: CDNS: Develops computational software and hardware for electronic system design.
1+ YOEBachelor's or Master's in Electrical/Electronics Engineering, 1+ years related experience, strong background in signal, power, and electromagnetics for package and PCB design, excellent communication and presentation skills.
Sigrity, Clarity, PCB Editor, ICP, Cadence Allegro
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1w
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Physical Design - SOC Top Lead
San Jose or Pittsburgh or Austin
$200k-$250k/yr OnsiteFull Time
Efficient Computer
Efficient Computer: Developing ultra-low-power general-purpose processors for edge AI computing.
8+ YOEEnd-to-end SOC top ownership including full-chip integration, timing closure, power/PDN analysis, physical verification, SI, clock/reset, DFT, package co-design, and tapeout readiness; advanced degree in EE and extensive PD experience.
Innovus, ICC2, Tempus, PrimeTime, RedHawk, Calibre, Voltus, TCL, shell, python
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6d
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Optical Engineer (52249)
Milpitas, California, United States
$121k-$178k/yr OnsiteFull Time
Headway Technologies
Headway Technologies: Designs and manufactures magnetic recording heads for hard disk drives
2+ YOEMaster’s degree in optical or electrical engineering, applied physics, or equivalent experience; 2+ years in optics or related fields; optical testing, laser package design, modeling, simulation, and failure analysis experience.
Lumerical, Tidy3D, COMSOL, Claude, ChatGPT, TEM, EELS, EDS, SIMS, XPS, Microsoft Office
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2mo
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Signal Integrity & Power Integrity Principal Engineer
San Jose, California, United States
$187k-$270k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
15+ YOE15+ years SI/PI experience; Bachelor's in Electrical/Computer Engineering; expertise in SI/PI for silicon/package/board; strong with HFSS/HSPICE/Sigrity/ADS; scripting in Python/MATLAB; design tool experience
ANSYS HFSS, Synopsys HSPICE, Cadence Sigrity, Keysight ADS, Mentor Graphics, Cadence Allegro, Python, MATLAB
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2w
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Sr. Signal Integrity/Power Integrity Engineer
Santa Clara, California, United States
OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
10+ YOEExtensive experience in high-speed signal and power integrity, PCB/package design, proficiency in SI/PI tools and lab test equipment, Master/PhD in EE/CE, strong problem-solving and cross-functional collaboration skills.
IBIS-AMI, SPICE, Keysight ADS, Cadence Sigrity, Ansys HFSS, MATLAB, Python, TDR, VNA, High-Speed Oscilloscopes, Spectrum Analyzer
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