Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
1mo
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Memory Packaging Engineer
San Jose or San Diego
$180k-$272k/yr OnsiteFull Time
8+ YOELead memory packaging development for 2.5D/3D and HBM/IPM solutions; supply chain and partner management; failure analysis and product integration to mass production.
1mo
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Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
2mo
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Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
TransPak: Packaging solutions provider
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
1mo
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Flexible Packaging Engineer - Destiny Packaging |Salinas, CA
Salinas, California, United States
$75k-$80k/yr HybridFull Time
Knowledge of flexible packaging films and structures, Excel and presentation skills, ability to support sales and customers, bachelor's degree preferred, travel as needed; 2 years field experience preferred.
Microsoft PowerPoint, Keynote, Microsoft Excel
2mo
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Senior IC Packaging Engineer
San Jose, California, United States
OnsiteFull Time
10+ YOESenior IC Packaging Engineer with 10+ years in IC packaging, expertise in FC BGA, SiP, RDL, and chiplet architectures, and leadership in packaging programs.
Cadence Allegro Package Designer (APD), HFSS, SIwave, Ansys Designer, Flip-Chip BGA, SiP, RDL, UCIe, PCIe, LPDDR5, LPDDR5X
22h
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Integrated Circuit Packaging Architect Engineer
San Jose, California, United States
$183k-$314k/yr HybridFull Time
Proven semiconductor technology development and leadership experience in package architecture, process definition, DFM/DFY, and yield improvement; strong communication skills; BS/MS/PhD in related fields.
2mo
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Photonic Packaging Engineer, Principal
San Jose, California, United States
OnsiteFull Time
10+ YOEPh.D. or M.S. in EE, Physics, Materials Science, Mechanical Engineering, or related field; 10+ years in photonic packaging or related areas; strong expertise in high-speed packaging, thermal management, and optomechanical design.
3mo
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Packaging Product Design Engineer
Cupertino, California, United States
OnsiteFull Time
5+ YOE5 years experience; BS in Mechanical Engineering or Packaging Science; 3D/2D CAD; strong engineering fundamentals; travel up to 20%.
3D CAD, 2D CAD, FEA
2mo
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Software Engineer 6 - Ads Pricing & Packaging
Los Gatos or New York
$499k-$900k/yr OnsiteFull Time
10+ YOE10+ years software development experience (5+ years on inventory management); expertise in yield optimization, dynamic pricing, auction mechanics, rate card and packaging systems; API and data model design; technical leadership and strong communication.
VAST, OpenRTB
5d
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Staff Engineer, Packaging Mechanical Simulation
San Jose, California, United States
$163k-$253k/yr OnsiteFull Time
3+ YOEPhD in engineering discipline, 3+ years modeling/simulation experience in semiconductors, expertise in mechanical/thermal modeling, strong technical writing and collaboration skills.
ANSYS, Abaqus, HyperMesh, Python, MATLAB, ANSYS APDL
2mo
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Software Engineer 6 - Ads Pricing & Packaging
Los Gatos or New York
$499k-$900k/yr OnsiteFull Time
10+ YOE10+ years software development; 5+ years in inventory management and yield optimization; experience with dynamic pricing, rate cards, and auction mechanics; strong leadership and communication skills.
Programming, API Design, Data Modeling, Advertising Technology, Auction Systems, Rate Card Management, Inventory Management Systems
1mo
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ASIC Packaging Signal/Power Integrity Engineer (Hybrid)
San Jose, California, United States
$153k-$219k/yr OnsiteFull Time
0+ YOEDegree in Electrical Engineering (BS/MS/PhD) with relevant SI/PI experience; expertise in high-speed signaling, SI/PI simulation and layout review using industry EDA tools; strong communication and technical problem-solving skills.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, IBIS, Vector Network Analysis
1mo
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Staff Software Engineer, Pricing and Packaging Engineering
San Francisco or Denver or New York City or San Jose
$197k-$247k/yr HybridFull Time
8+ YOE8+ years building large-scale backend platform systems (commerce/billing/subscriptions preferred); strong distributed systems, API design, SLO, and mentorship experience; proven delivery of multi-quarter projects.
3w
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Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
2mo
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Staff Engineer, Build & Toolchain Infrastructure
San Jose, California, United States
$172k-$258k/yr OnsiteFull Time
6+ YOELead build/toolchain architecture for reproducible builds, hermetic environments, packaging, and developer productivity; 6+ years Linux distributed systems; bachelor’s in CS/engineering.
Linux, Build systems, Toolchains, Packaging, Artifact management
1mo
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Senior Package Design Engineer
San Jose or Taipei
$111k-$206k/yr HybridFull Time
5+ YOEMS in EE/CE, 5+ years packaging design/layout experience, proficiency with Cadence Allegro Package Designer (APD) and AutoCAD, experience with multiple package types and high-speed routing, knowledge of substrate technologies and JEDEC standards.
Cadence Allegro Package Designer (APD), AutoCAD
5d
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Principal Package Design Engineer
San Jose, California, United States
$195k-$240k/yr HybridFull Time
5+ YOEMSc/PhD in engineering, 5+ years semiconductor packaging experience, expertise in advanced packaging architectures, reliability testing, thermal/mechanical/electrical analysis, OSAT collaboration, and project leadership.
Cadence Allegro Package Designer, Solid works, ANSYS, COMSOL, JMP, Minitab
3mo
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Senior Staff Product Engineer
San Jose, California, United States
$159k-$229k/yr OnsiteFull Time
12+ YOELead in product development; analyze data for yield and qualification; mentor team; strong background in analog/CMOS/GaN packaging.
GaN, LDMOS, Analog circuitry, Failure analysis, Data analysis, Matlab, Jira, Confluence, AI tools
1mo
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R&D Process Engineer, Advanced Bonding Process Development
San Jose or California
$125k-$145k/yr OnsiteFull Time
Bachelor's degree in materials science, electrical or chemical engineering (or advanced degree), experience in semiconductor packaging or process engineering preferred, familiarity with bonding, thin-film deposition, surface preparation, metrology, failure analysis, reliability testing, strong problem-solving and communication skills.
1mo
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R&D Engineer
San Jose, California, United States
$168k-$268k/yr OnsiteFull Time
12+ YOEMSEE +15 years or PhD +12 years in semiconductor process technology/advanced packaging. Expertise in advanced packaging, system-in-package assembly, reliability, yield analysis, thermal/stress simulation, and project management.
EFA, PFA