952 perl jobs at 180 companies in California
3mo
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CPU Physical Design and Integration Engineer
Santa Clara, California, United States
OnsiteFull Time
BS degree; experience with place-and-route and physical verification; scripting in Perl or Tcl.
Place and Route tools, PDV, DRC/LVS, Python, Perl, Tcl
2mo
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Applied Scientist II, Amazon AWS Agentic AI, AWS AI Fundamental Research
Santa Clara, California, United States
$172k-$222k/yr OnsiteFull Time
4+ YOEPhD or Masters with 4+ years in CS/ML; patents/publications; programming in C/C++, Python, Java or Perl.
C++, Python, Java, Perl
3mo
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Design Automation Engineer
San Jose, California, United States
$143k-$215k/yr OnsiteFull Time
8+ YOE8+ years in Static Timing Analysis, Liberty models, STA flow development, and scripting (Python, Perl, Tcl, Shell).
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Shell, Perl, Fusion Compiler, Innovus, Cadence Pegasus
3mo
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HBM SoC RTL Design Engineer
Folsom, California, United States
$146k-$297k/yr OnsiteFull Time
10+ YOE10+ years in electrical/computer engineering; SystemVerilog/Verilog; RTL-to-GDS flow; Cadence/Synopsys/Siemens; Python/TCL/Perl scripting.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl
1w
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CPU Performance Modeling Engineer (Multiple Levels)
Santa Clara or Austin
$167k-$251k/yr OnsiteFull Time
2+ YOERequires a relevant bachelor's, master's, or PhD and 2+ years of CPU architecture and programming experience; proficiency in C, C++, and Perl or Python is required.
C, C++, Perl, Python, RTL, MMU, SIMD
6d
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RTL Design Engineer, Silicon
Mountain View, California, United States
$138k-$197k/yr OnsiteFull Time
4+ YOEBachelor’s degree or equivalent practical experience; 4 years of IP development or integration; ASIC development with Verilog or VHDL; scripting with Perl or Python.
Verilog, VHDL, Perl, Python, Lint, CDC, FV, UPF, ASIC, FPGA
3mo
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Spark Engineer
Sunnyvale, California, United States
OnsiteFull Time
5+ YOE5+ years in software development; data engineering with pipelines; Python/Perl/Shell; Java; Oracle/MySQL; real-time pipelines with Kafka/Storm.
Python, Perl, Shell, Java, Oracle, MySQL, Kafka, Storm, HDFS, Hive, Pig, Oozie, HBase, Spark
3w
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Production Support Engineer - Utah
Salt Lake City or Arizona or California or Colorado or Connecticut or Delaware or Florida or Georgia or Illinois or Indiana or Massachusetts or Maryland or Minnesota or North Carolina or New Jersey or New York or Pennsylvania or Tennessee or Texas or Utah or Virginia
HybridFull Time
5+ YOE5+ years experience preferred; bachelor's in CS, Linux, scripting (Perl/Python/Unix shell), networking, database proficiency, strong troubleshooting and communication skills.
Linux, Perl, Python, UNIX, Multicast, TCP/IP, UDP, SNMP, Autosys, Perforce, ClearCase
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOE10+ years in VLSI design/verification; Verilog/SystemVerilog; UVM; Python, TCL, PERL or similar; C/C++; Bachelor’s or Master’s in Electrical or Computer Engineering.
Verilog, SystemVerilog, UVM, Python, C, C++, Specman, TCL, PERL
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOESenior verification engineer with 10+ years in VLSI design/verification; strong Verilog/SystemVerilog, UVM; scripting (Python, Perl, TCL); C/C++; leadership.
Verilog, SystemVerilog, UVM, Python, PERL, TCL, C, C++, Specman
1mo
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Data Scientist - TikTok Ads
San Jose, California, United States
$179k-$293k/yr OnsiteFull Time
3+ YOE3+ years quantitative analysis experience, BA/BS in a quantitative field, fluency in SQL and scripting (Python, PHP, Perl), strong communication and statistical understanding.
SQL, PHP, Python, Perl, Hive, Hadoop
3mo
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Technical Support Scientist, Probe Design
Newark, California, United States
$89k-$147k/yr OnsiteFull Time
5+ YOEPhD or MS with 3+ years in molecular biology or bioinformatics; 5+ years Linux, Python, Perl; sequencing; probe design; strong communication and troubleshooting skills.
Linux, Python, Perl, BLAST, BLAT, RNAscope, BaseScope, miRNAscope
1mo
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Principal SoC Integration Flow Architect - Automation
San Jose or San Diego
$211k-$286k/yr OnsiteFull Time
8+ YOEExpertise in SoC integration and RTL design, scripting (Python/Perl/Tcl/C++), familiarity with IP-XACT and EDA integration; 8+ years experience preferred.
Python, Perl, Tcl, C++, IP-XACT, Verilog, SystemVerilog
3mo
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Senior Power Analysis and Optimization Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOEMS with 5+ years or PhD with 3+ years in EE/CE/CS; strong power design knowledge; Verilog; experience with power tools; Python/Perl/C++.
Verilog, PowerArtist, PrimePower, PrimePower RTL, RTL Architect, Python, Perl, C++
2mo
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Post-silicon Validation and Debug Engineer
Hillsboro or Folsom
$106k-$200k/yr OnsiteFull Time
3+ YOEBachelor's or master's in EE/CE/CS with post-silicon validation and CPU/SoC experience; scripting in Python/C/C++/Perl; hardware debugging tools knowledge.
Python, C, C++, Perl, Logic analyzers, Oscilloscopes
1w
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Austin or Westford or Durham or California
$136k-$265k/yr HybridFull Time
5+ YOEBachelor's or master's degree in engineering or computer science, 5+ years' experience, ASIC workflows, UVM, Verilog/SystemVerilog, simulation tools, and Python, Perl, or systems programming.
Python, Perl, Verilog, SystemVerilog, UVM, VCS, Verdi, Xcelium
3mo
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Principal Physical Design Engineer, STA
San Jose, California, United States
$209k-$250k/yr OnsiteFull Time
10+ YOE10+ years in timing analysis and sign-off for complex SoCs; Cadence/Synopsys flows; 7nm or below; scripting (Tcl/Python/Perl); able to work independently.
Cadence, Synopsys, Tcl, Python, Perl, SystemVerilog
5d
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Silicon Design Engineer
Santa Clara, California, United States
OnsiteFull Time
0+ YOEMaster’s degree in computer, electronic, or electrical engineering or related field; experience with Verilog, SystemVerilog or VHDL, RTL, Python or Perl, ASIC tools, and Unix or Linux environments.
Verilog, SystemVerilog, VHDL, Python, Perl, ASIC, Unix, Linux
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOE10+ years in VLSI design/verification; FPGA/EDA; Verilog/SystemVerilog; scripting (Python, TCL, PERL); C/C++; UVM; BS or MS in EE/CS.
Verilog, SystemVerilog, UVM, EDA, C, C++, Python, Perl, TCL
3mo
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Senior Static Timing Analysis (STA) Methodology Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior STA/Timing methodology engineer with 8+ years in STA, scripting (Tcl/Python/Perl), signoff; BS/MS in ECE or related; onsite in Saratoga, CA.
PrimeTime, PT-SI, PT-PX, PT-ECO, Tcl, Python, Perl
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