329 perl jobs at 56 companies in Leander, TX
1mo
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Senior Software Development Engineer
Austin or United States
$120k/yr HybridFull Time, Temporary
5+ YOEU.S. work authorization; bachelor’s in CS/IS/Engineering or equivalent; 5+ years experience with frontend (Perl CGI, JavaScript, CSS, HTML), middleware (Python, Perl, Java), and SQL; proficient on Linux; strong communication and mentoring skills.
Linux, Perl CGI, JavaScript, CSS, HTML, Python, Perl, Java, SQL, LAMP, Angular, Debian, Ubuntu, RedHat, Ansible
3mo
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Graphics Post silicon Test & Methodology Engineer
Austin, Texas, United States
OnsiteFull Time
3+ YOEBS + 3 years; experience with DFT-ATPG/BIST; Perl or Python; device physics; STA understanding is a plus.
Perl, Python, JMP
3d
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CPU Performance Modeling Engineer (Multiple Levels)
Santa Clara or Austin
$167k-$251k/yr OnsiteFull Time
2+ YOERequires a relevant bachelor's, master's, or PhD and 2+ years of CPU architecture and programming experience; proficiency in C, C++, and Perl or Python is required.
C, C++, Perl, Python, RTL, MMU, SIMD
1mo
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Systems Power Design Engineer
Austin, Texas, United States
$117k-$200k/yr HybridFull Time
Experience in system power modeling, scripting (C/C++, Perl, Ruby, Python), lab debugging with analyzers/oscilloscopes, and a Bachelors (or Masters) in electrical or computer engineering.
C, C++, Perl, Ruby, Python, Logic analyzer, Protocol analyzer, Oscilloscope
2w
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SDE, MLA hardware/software co-design, Annapurna Labs Machine Learning Acceleration
Austin, Texas, United States
$136k-$184k/yr OnsiteFull Time
Bachelor's in Electrical Engineering or related, strong debugging across IP-to-SoC levels, experience in embedded/software or chip design; Python or Perl scripting preferred.
Python, Perl
2mo
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Senior Power Analysis and Optimization Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOEMS with 5+ years or PhD with 3+ years in EE/CE/CS; strong power design knowledge; Verilog; experience with power tools; Python/Perl/C++.
Verilog, PowerArtist, PrimePower, PrimePower RTL, RTL Architect, Python, Perl, C++
16h
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CPU Emulation Engineer, Silicon
Austin or Mountain View or Portland or Poughkeepsie
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent practical experience; 8 years with emulation or FPGA platforms; RTL design using Verilog or SystemVerilog; scripting with Python, Perl, TCL, or Makefiles.
Synopsys ZeBu, HAPS, Cadence Palladium, Protium, Siemens Veloce, Verilog, SystemVerilog, Python, Perl, TCL, Makefiles, Field-Programmable Gate Array (FPGA), Register-Transfer Level (RTL)
7h
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Graduate Digital Design Electrical Engineer
Austin, Texas, United States
OnsiteFull Time
Recent BSc/MSc graduate in electrical or computer engineering with SystemVerilog test-bench debugging, Python or Perl scripting, analytical skills, and strong written and verbal communication.
SystemVerilog, Python, Perl, Cadence, Synopsys, SimVision, Verdi, ARM Cortex-M
2w
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Senior Site Reliability Engineer
Reston or Austin
$81k-$187k/yr OnsiteFull Time
3+ YOERequires 3+ years SRE/operations experience, deep Linux knowledge, scripting and automation (Python, Bash, Perl, Java, Go), and TS/SCI clearance for US applicants.
Linux, Unix, Docker, Kubernetes, Terraform, Python, Bash, Perl, Java, Go, Ruby, JavaScript, Chef, Puppet
2mo
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Sr. Modem Design Verification Engineer
Austin, Texas, United States
$125k-$231k/yr OnsiteFull Time
5+ YOEBSEE/CE required, 5+ years digital design verification experience (modem/PHY preferred), SystemVerilog/UVM, scripting (Python/Perl), strong debugging and verification methodology skills.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Python, Perl, C/C++, MATLAB
1mo
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Test Engineer
Austin, Texas, United States
OnsiteFull Time
Experience developing and supporting electronic and software test programs, instrument drivers, test plans, failure analysis, and coordinating test development; familiarity with Python, Lab View, or Perl preferred.
Python, Lab View, Perl
2mo
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Sr. Modem Design Verification Engineer
Austin, Texas, United States
$125k-$231k/yr OnsiteFull Time
5+ YOEBachelors in EE/CE or related; 5+ years verification experience (modem/PHY preferred); SystemVerilog and UVM experience; scripting with Python/Perl; strong debugging and wireless/DSP knowledge.
SystemVerilog, UVM, SystemVerilog assertions (SVA), Python, Perl, C/C++, MATLAB
2mo
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SOC Design Engineer, ASIC Tools and Methodology Development
Austin, Texas, United States
$116k-$219k/yr HybridFull Time
3+ YOEBachelor's or Master's in EE/CE (or equivalent), 3+ years experience preferred, hands-on Verilog, Python/Perl scripting, Unix/Linux shell and Makefiles, strong collaboration and communication skills.
Verilog, Python, Perl, Unix/Linux shell scripting, Makefiles
9h
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Physical Design Engineer, AI Accelerator IP
Austin or Belgrade or Toronto
$100k-$500k/yr HybridFull Time
5+ YOEBS, MS, or PhD in EE, ECE, CE, CS; 5+ years of physical design experience through tapeout; expertise with Innovus, ICC2/FusionCompiler, PrimeTime, Tcl, Python, and Perl.
Innovus, ICC2, Fusion Compiler, PrimeTime, Tcl, Python, Perl, UPF, STA, LEC, LEF, DEF, GDSII
1mo
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
3w
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Senior Physical Design Engineer
Austin, Texas, United States
$129k-$217k/yr OnsiteFull Time
5+ YOEPerform APR and PV signoff for advanced-node CPU designs; strong scripting (Perl, Python, TCL, Make); 5+ years APR experience; knowledge of floorplanning, CTS, routing, signoff.
Perl, Python, TCL, Make
1mo
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Austin Hiring Event - Senior Staff Physical Design Engineer
Austin, Texas, United States
$133k-$196k/yr OnsiteFull Time
5+ YOEBachelor's in CS/EE,5+ years physical design experience, RTL-to-GDS knowledge, scripting in Shell/Perl/TCL/Python, familiarity with static timing, EM/IR and verification tools.
Shell, Python, TCL, Perl, Verilog, Tempus, PrimeTime, Voltus, PrimeRail, Calibre, LEC, Formality, Cadence Innovus
1mo
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IP Verification Engineer (785654)
Austin, Texas, United States
OnsiteFull Time
Several years of industry RTL verification experience, strong SystemVerilog/UVM, testbench architecture, TLM modeling, HW emulation, scripting (TCL/Python/Perl), and BS/MS in EE or CE.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF, C, assembly
2mo
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Electrical Engineer 2 (Austin, TX, US)
Austin, Texas, United States
$78k-$143k/yr OnsiteFull Time
MS with digital IC design experience; ability to develop RTL, work in HDL synthesis environments; scripting (Python, Perl, Tcl, shell); SystemVerilog/UVM and digital verification experience desirable.
Perl, Python, Tcl, shell, MATLAB, C, SKILL, SVN, SOS, SystemVerilog, UVM, SPI, I2C, RTL, HDL
3mo
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Principal Engineer, GPU Design Verification (Subsystems)
San Jose or Austin
$222k-$365k/yr OnsiteFull Time
10+ YOE15+ years exp; 10+ years in GPU/semiconductor verification; strong C/C++, Python/Perl; SystemVerilog/UVM; testbench design; multiple subsystem verification; excellent debugging and collaboration.
SystemVerilog, UVM, C++, Python, Perl