15 physical asic design implementation engineer jobs at 7 companies in United States
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ASIC Implementation Engineer
San Jose, California, United States
$144k-$230k/yrOnsiteFull Time
Broadcom Inc.NASDAQ: AVGO: Global technology leader in semiconductors and infrastructure software.
10+ YOETop-level floorplanning and chip integration expertise, experience resolving physical design DRC/LVS/EMIR issues, scripting in Python/Tcl/Perl, familiarity with EDA tools, 10+ years of relevant ASIC physical design experience; must work onsite in San Jose.
MetaNASDAQ: META: Builds technologies that help people connect, find communities, and grow businesses.
8+ YOEBachelor's degree (or equivalent) and 8+ years in ASIC physical design with end-to-end implementation, experience with industry EDA tools, static timing analysis and multi-corner closure at advanced nodes (7nm or below); scripting and low-power experience preferred.
Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre, Python, Tcl
Qualcomm Technologies, Inc.: Developing semiconductor, wireless, connectivity, automotive, AI, and computing technologies for device and enterprise customers.
4+ YOERequires a relevant bachelor's degree with 6+ years, master's with 5+ years, or PhD with 4+ years; expertise in ASIC implementation, synthesis, physical design, signoff tools, sub-micron tape-outs, and scripting.
Qualcomm Technologies, Inc.: Developing semiconductor, wireless, connectivity, automotive, AI, and computing technologies for device and enterprise customers.
2+ YOEBachelor's or master's degree in a technical field and 2+ years of physical design or related experience, or equivalent advanced degree. Experience with ASIC/SoC implementation and physical design workflows required.
Micron TechnologyNASDAQ: MU: Global leader in memory and storage semiconductor solutions.
8+ YOEMaster's in electrical engineering with 8+ years, or bachelor's with 10+ years in ASIC physical design; expertise in implementation, signoff, power integrity, scripting, and technical leadership.
Synopsys IC Compiler II, Fusion Compiler, PrimeTime, PrimePower, RedHawk, Python, Tcl, AI-assisted technologies, Generative AI tools
NVIDIANASDAQ: NVDA: Computing platform for AI and accelerated graphics.
5+ YOEBachelors in EE/CE/CS (or equivalent) and 5+ years experience; strong Verilog/SystemVerilog skills, RTL/micro-architecture experience, Python/Perl scripting, understanding of physical implementation and VLSI.
NVIDIANASDAQ: NVDA: Computing platform for AI and accelerated graphics.
5+ YOEBachelor's or Master's in EE/CE/CS (or equivalent) with 5+ years industry experience; strong Verilog/SystemVerilog and RTL/microarchitecture experience; scripting in Perl or Python; understanding of physical implementation and VLSI.
Micron TechnologyNASDAQ: MU: Global leader in memory and storage semiconductor solutions.
8+ YOEMaster's degree with 8+ years or bachelor's degree with 10+ years in ASIC physical design; expertise in implementation, signoff, power integrity, scripting, automation, and technical leadership.
Synopsys IC Compiler II (ICC2), Fusion Compiler, PrimeTime, PrimePower, RedHawk, Python, Tcl, Generative AI
Kuiper SystemsNasdaq Global Select Market: AMZN: Developing a low Earth orbit satellite network to deliver high-speed, low-latency broadband internet connectivity.
7+ YOEBachelor's degree in computer science, computer engineering, or electrical engineering and 7+ years of ASIC implementation experience, including synthesis, STA, DFT, and P&R.
Kuiper SystemsNasdaq Global Select Market: AMZN: Developing a low Earth orbit satellite network to deliver high-speed, low-latency broadband internet connectivity.
7+ YOEBachelor's degree in electrical engineering or related field and 7+ years of ASIC implementation experience, including synthesis, STA, DFT, and place-and-route for deep sub-micron nodes.
Kuiper SystemsNasdaq Global Select Market: AMZN: Developing a low Earth orbit satellite network to deliver high-speed, low-latency broadband internet connectivity.
7+ YOEBachelor's degree in Electrical Engineering or related field and 7+ years of ASIC implementation experience, including synthesis, STA, P&R, physical synthesis methodology, chip tape-outs, and multi-power-island designs.
Principal CPU Physical Design Engineer (San Diego, CA)
San Diego, California, United States
$212k-$318k/yrOnsiteFull Time
Qualcomm Technologies, Inc.: Developing semiconductor, wireless, connectivity, automotive, AI, and computing technologies for device and enterprise customers.
10+ YOE10+ years ASIC/SoC physical design experience; strong RTL-to-GDSII implementation skills, timing closure, power and area optimization; scripting with TCL or Python; experience with Synopsys/Cadence and advanced nodes preferred.
NVIDIANASDAQ: NVDA: Computing platform for AI and accelerated graphics.
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
DASH Tech Integrated Circuits: Private U.S. semiconductor startup developing flexible, efficient system-on-chip processors for embedded sensing and communications applications.
5+ YOE5+ years semiconductor engineering with leadership across analog, digital (RTL), mixed-signal, and physical implementation; proven SoC/ASIC tape-out and silicon bring-up experience; B.S. in ECE or equivalent; strong operational and communication skills.