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Senior Design Lead - Physical Design (96945)
United States
OnsiteFull Time
Advanced proficiency in physical design tools and methodologies, strong UX knowledge, leadership experience overseeing multiple design teams, stakeholder communication, and research on industry trends; CPD/CUXP certifications are valuable.
UCIe
3mo
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Physical Design Engineer
Cupertino or United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with high PHY/SOC design and physical design tooling preferred.
Verilog, Perl, Tcl, GDSII, Place & Route tools
2mo
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Physical Design Engineer
Mountain View, California, United States
$230k-$400k/yr OnsiteFull Time
8+ YOE8+ years in physical design for high-performance chips at advanced nodes, expert across full physical design flow, hands-on with industry PD and signoff tools, and ability to collaborate with architects, RTL designers, EDA vendors, and foundries.
Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Tempus
2w
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Physical Design Engineer
San Jose, California, United States
$150k-$250k/yr OnsiteFull Time
7+ YOE7+ years physical design experience (synthesis, PnR, STA, timing convergence, physical verification); Bachelor's in EE/CE/CS or equivalent experience; proficiency with Innovus, Tempus, Quantus, TCL; experience with EM/IR, PDN, LEC and sub-7nm/SoC design.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
1w
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Principal Physical Design Engineer , Data Center Engineering
Seattle, Washington, United States
$163k-$220k/yr OnsiteFull Time, Part Time
10+ YOEBachelor's in architecture/construction/engineering, 10+ years in mission-critical facilities, experience in concept design, permitting, construction execution, building systems integration; RA or PE preferred.
DFMA
1mo
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Physical Design Engineer
Sunnyvale, California, United States
$230k-$280k/yr OnsiteFull Time
10+ YOE10+ years physical design experience; expertise in full-chip physical verification, DRC/LVS resolution with ICV or Calibre, IR/EM analysis, 3D/2.5D packaging and die stacking; scripting with Tcl and Python; familiarity with Synopsys tools.
Synopsys, ICV, Calibre, Tcl, Python
2mo
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Physical Design Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
BS/MS/PhD in EE/ECE/CE/CS with experience in synthesis, PnR, timing closure; proficient with FusionCompiler, PrimeTime, RedHawk; scripting Tcl, Perl, Python; knowledge of low-power design; drive physical design from architecture to signoff.
FusionCompiler, PrimeTime, RedHawk, Tcl, Perl, Python
1w
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Director, Product Design (Physical Products)
Mountain View, California, United States
$190k-$205k/yr HybridFull Time
10+ YOE10+ years designing and shipping physical consumer products; deep 3D CAD and manufacturing expertise; experience with injection-molded plastics, mechanisms, prototyping, and supplier/manufacturer partnerships; design leadership experience.
SolidWorks, Fusion 360, Creo, 3D printing, laser cutting
2w
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Physical Design Engineer
Massachusetts or Phoenix
$91k-$149k/yr OnsiteFull Time
0+ YOEDesign and implement physical IC/SoC from RTL to GDS, perform synthesis/place-and-route/CTS/STA, power and noise analysis, verification and optimization using EDA tools.
EDA tools, TCL
4d
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Physical Design Engineer
Colorado Springs, Colorado, United States
$129k-$207k/yr OnsiteFull Time
12+ YOEBachelor's in Electrical/Electronics Engineering, 12+ years' RTL-to-tapeout physical design experience, TCL/PERL scripting, EDA tool proficiency, B2B communication and timing closure expertise.
TCL, PERL, EDA Tools
1mo
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Physical Design Engineer
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
3+ YOEBSEE/MSEE or equivalent; 3+ years in VLSI physical design on 5nm-3nm; strong P&R, timing, IR drop; scripting in Python/Perl/Tcl; experience with Synopsys and Cadence tools.
Synopsys ICC2, Synopsys DC, Synopsys PT, Synopsys STAR, Synopsys ICV, Cadence Genus, Cadence Innovus, Cadence Tempus, Python, Perl, Tcl, Make
1mo
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Physical Design Engineer
Austin or New York City or New York or Washington or Illinois or United States or Canada
$137k-$201k/yr OnsiteFull Time
7+ YOEDegree in Electrical/Computer Engineering plus multi-year ASIC/physical design experience; experience with RTL-to-GDSII flow, STA, floorplanning, timing closure, and EDA tools (Innovus, PrimeTime, Tempus, Calibre, Redhawk/Voltus).
Innovus, Tempus, PrimeTime, Tweaker, Redhawk, Voltus, Calibre, Pegasus, Python
3w
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Physical Design Intern
San Jose, California, United States
$35-$45/hr OnsiteInternship
Currently pursuing a BS/MS in EE/CE or related field; foundational VLSI and ASIC physical design knowledge; scripting experience (Python, Perl, TCL); familiarity with ASIC flow and strong analytical/problem-solving skills.
Python, Perl, TCL, Synopsys ICC2, Cadence Innovus, PrimeTime, Tempus, LEF/DEF, UPF/CPF, GPT, Copilot
1mo
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Physical Design Engineer
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
3+ YOEBSEE/MSEE or equivalent; 3+ years VLSI physical design on 5/4/3nm; expertise in P&R, timing closure, power/clock distribution, verification; experience with Synopsys/Cadence EDA tools; Python/Perl/Tcl/Make scripting.
ICC2, DC, PT, STAR, ICV, Genus, Innovus, Tempus, Python, Perl, Tcl, Make
2w
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Physical Design Technical Lead
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
15+ YOE4+ MgmtMaster's in EE/CE plus 15+ years physical design experience, 4+ years technical lead experience, hands-on tapeout ownership, expertise with Synopsys/Cadence toolchains, STA, power/EMIR, UPF/CPF, Tcl/Python scripting, and ML/AI-driven physical-design workflows.
Synopsys Fusion Compiler, Cadence Innovus, Synopsys PrimeTime, Ansys RedHawk, Cadence Voltus, Mentor Calibre, Cadence PVS, Synopsys DSO.ai, Fusion Compiler AI, Cadence Cerebrus, Tcl, Python, Perl
2w
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Silicon Physical Design Engineer
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's in CS/CE or equivalent, 8+ years physical design implementation for digital SoCs, experience with advanced nodes (3nm or below), EDA tools, timing/power/physical verification, and methodology development.
EDA tools, Python, Tcl
1mo
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Principal Physical Design Engineer
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CompEng, 7+ years ASIC physical design experience, strong expertise with Cadence Innovus and Synopsys Fusion Compiler, scripting in Tcl/Python/Linux shell, and physical signoff knowledge.
Cadence Innovus, Synopsys Fusion Compiler, Tcl, Python, Make, Linux shell, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Git, Perforce
1mo
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Principal Physical Design Engineer
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CE or related, 7+ years ASIC physical design/methodology experience, expertise with Cadence Innovus and/or Synopsys Fusion Compiler, strong scripting (Tcl, Python, Linux shell), and physical signoff knowledge.
Cadence Innovus, Synopsys Fusion Compiler, Tcl, Python, Make, Linux shell, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Git, Perforce
1mo
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Staff Engineer - Physical Design
Singapore or Austin or Hsinchu or Shanghai or Shenzhen
OnsiteFull Time
8+ YOEMaster's or Bachelor's in EE/CE, 8+ years IC physical design experience, expertise in floorplanning/placement/CTS/routing/physical verification, hands-on with Cadence Innovus and/or Synopsys Fusion Compiler, TCL scripting, English and Mandarin required.
EDA, Cadence Innovus, Synopsys Fusion Compiler, Cadence, Synopsys, TCL, Python
2mo
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Senior Physical Design Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior Physical Design Engineer with 8+ years in ASIC/SoC physical design; Cadence Innovus expertise; floorplanning, CTS, routing; timing closure; scripting (Python/Tcl).
Cadence Innovus, Synopsys ICC2, Mentor Calibre, Tcl, Python, Verilog, SystemVerilog, UVM, VHDL
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