San Francisco • 50 milesRemote · Hybrid · Onsite · Field · All Environments
San Francisco • 50 milesRemote · Hybrid · Onsite · Field · All Environments
San Francisco • 50 milesRemote · Hybrid · Onsite · Field · All Environments
San Francisco • 50 milesRemote · Hybrid · Onsite · Field · All Environments
65 post silicon validation engineer jobs at 26 companies in San Francisco, CA
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Lead Post-Silicon Validation Engineer
Santa Clara, California, United States
OnsiteFull Time
12+ YOELead post-silicon bringup and memory system validation for GPU products; 12+ years in memory systems; experience with DRAM/HBM/GDDR/LPDDR; strong communication and leadership.
SystemC, C++
3w
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Silicon Validation Engineer, Infra Silicon
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
8+ YOE8+ years in silicon validation or post-silicon bring-up for custom ASICs/accelerators; experience with pre- and post-silicon validation, lab debug tools, and automation using Python/C/C++; bachelor's in CS/CE or equivalent.
Python, C, C++, RTL simulation, emulation platforms, FPGA prototyping, logic analyzers, oscilloscopes, JTAG, protocol analyzers, PCIe, DDR, BMC
2w
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Silicon Validation Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Hands-on silicon validation and post-silicon bring-up experience; SoC/accelerator validation; debug across RTL/firmware/software/board; C/C++ and Python familiarity; lab and emulation experience; must be authorized to work in the US and work from Mountain View office Tue-Thu.
Cadence Palladium, SystemVerilog, UVM, Python, C, C++, JTAG, Oscilloscope, Logic Analyzer, Protocol Analyzer
2mo
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PMU Silicon Validation Engineer
Cupertino, California, United States
OnsiteFull Time
Post-silicon bring-up, debug, and validation of analog and power ICs; strong engineering fundamentals and collaboration with IC designers and product teams.
1mo
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AI Silicon, Silicon Validation Engineer
Palo Alto, California, United States
OnsiteFull Time
5+ YOEB.S. or M.S. in EE/CE or related field,5+ years post-silicon bring-up or hardware validation experience,proficiency with lab test equipment,mixed-signal characterization,and Python for lab automation.
Python, Oscilloscope, Logic Analyzer, Power Analyzer, FPGA, RTL
1mo
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Sr. Engineer, Silicon Validation
San Jose, California, United States
$150k-$193k/yr OnsiteFull Time
3+ YOEBachelor's in EE or related, 3+ years post-silicon bringup/validation experience, SerDes and mixed-signal characterization, Python scripting, lab equipment proficiency, strong troubleshooting.
BERT, Oscilloscope/DCA, OSA, signal generators, Python, Git, JTAG, I2C, SPI
2mo
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Post-Silicon Validation - Senior Engineer
San Jose or California
$92k-$126k/yr HybridFull Time
Bachelor's degree in Electronics/Electrical/Systems Engineering, strong Python and instrumentation skills, familiarity with Jenkins, MATLAB/Pyplot, IEEE 802.3 and serial protocols (MDIO/SPI/I2C); lab hardware debugging and data analysis experience.
oscilloscopes, multimeters, thermal probes, digital power supplies, TDR, network analyzer, spectrum analyzer, logic analyzer, Python, Jenkins, Microsoft 365, Pyplot, Pyplotor, MATLAB, IEEE 802.3, MDIO, SPI, I2C
3w
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Hardware & Silicon Validation Principal Engineer
Santa Clara, California, United States
$151k-$226k/yr OnsiteFull Time
5+ YOEDegree in CS/EE (BS/MS/PhD) with 5–15 years experience, hands-on lab bring-up, post-silicon validation, debugging skills, scripting (Python/Perl/Shell), C/C++, FPGA prototyping, and familiarity with high-speed interfaces and Linux.
oscilloscopes, logic analyzers, protocol analyzers, Python, Perl, Shell, C/C++, Linux, FPGA, simulation, emulation, PCIe, Ethernet
2mo
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Senior Hardware Post-Silicon Validation Engineer (Hybrid)
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
8+ YOE8+ years post-silicon electrical validation experience; degree in electrical/computer engineering; hands-on silicon bring-up, signal/power integrity, high-speed measurements, and lab automation (Python) skills.
Python, oscilloscopes, logic analyzers, VNAs, protocol analyzers, BERTs, multimeters
3w
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Principal Silicon Engineer
Mountain View or Austin or Hillsboro or Redmond or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOEPhD/MS/BS in EE/CE/CS or related with relevant years of experience, strong PLL and high-speed clocking expertise, post-silicon validation skills, scripting (Python/Perl), Matlab/Simulink knowledge, and ability to pass Microsoft security/export screenings.
Python, Perl, Matlab (Simulink), Analog Behavioural Modeling (ABM)
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Firmware Engineer - Post-Silicon Validation
Mountain View, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOEBachelor's or Master's in engineering/computer science, 3+ years firmware/embedded experience, strong C/C++ and Linux skills, Python or shell scripting, hardware/software integration and debugging experience.
C/C++, Linux, Python
2w
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PCIe, CXL and Highspeed IO Validation Engineer
Austin or Santa Clara
$170k-$292k/yr HybridFull Time
5+ YOEPrincipal validation engineer with 5+ years experience in SoC post-silicon validation for high-speed IO (PCIe/CXL/UCIe), lab debug, test-plan development, scripting (C/C++,Python,Perl), and server OS experience.
PCIe, CXL, UCIe, C, C++, Python, Perl, Linux, Windows, protocol analyzer, logic analyzer, oscilloscope
1mo
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SoC Test Infrastructure Engineer, Post Silicon NPI
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent,8 years test engineering experience, proficiency in Python/Java/C#/C/C++, Advantest or Teradyne experience, ATE and pre/post-silicon validation experience.
Python, Java, C#, C/C++, Advantest, Teradyne, Automated Test Equipment (ATE)
1mo
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Senior Principal Post-Silicon Technical Program Manager, AI Connectivity Products
San Jose, California, United States
$205k-$250k/yr OnsiteFull Time
10+ YOE10+ years in semiconductor or systems engineering/program management; post-silicon validation and bring-up experience; strong cross-functional leadership; experience with firmware development, JIRA, Confluence; deep technical knowledge of PCIe, CXL, SerDes, Ethernet, NVMe.
JIRA, Confluence, COSMOS, PCIe, Ethernet, CXL, NVMe, NVLink, SerDes, ATE
2mo
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Sr. ASIC DFT Engineer (Silicon)
Sunnyvale or Austin or Irvine
$135k-$185k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical or computer engineering or physics; 5+ years in DFT/post-silicon validation; strong scripting and test automation.
Perl, Python, Tcl, C++, Siemens Tessent
1w
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Technical Lead - Post Silicon Validation (148456)
Fremont, California, United States
OnsiteFull Time
8+ YOE8+ years developing scalable code, network analysis, test automation, distributed systems, TDD, version control, CI/CD, and listed programming/database technologies.
Python, Ansible, Shell Script, Postgres, MSSQL, SQLite, Test Driven Development (TDD), version control systems, CI/CD pipelines, Docker, REST APIs
1w
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FPGA Engineer (eInfochips Inc)
Mountain View, California, United States
OnsiteFull Time
Experience with FPGA prototyping, C/C++ test content, SystemVerilog, Python, post-silicon validation, hardware debugging, verification, industry protocols, and cross-functional engineering collaboration.
C, C++, SystemVerilog, HAPS, Xilinx, Python, Perl, Ruby, JTAG, logic analyzers, oscilloscopes, multimeters, AMBA, AXI, AHB, APB, SPI, I2C, I3C, USB
2mo
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Principal Engineer, Hardware Design (AI2518)
San Jose, California, United States
$204k-$316k/yr OnsiteFull Time
10+ YOEMaster's in EE/CE, 10+ years ASIC design experience with block-level RTL (Verilog/SystemVerilog), synthesis, timing closure, DFT, silicon bring-up and post-silicon validation using lab equipment.
Verilog, SystemVerilog, PCIe, UCIe, DFT, oscilloscope, logic analyzer, protocol analyzer
2mo
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Principal Engineer - Digital ASIC Design
San Jose, California, United States
$70k-$163k/yr OnsiteFull Time
10+ YOE10+ years ASIC/FPGA digital design; SystemVerilog; Cadence/Synopsys front-end; PHY/Serdes knowledge; post-silicon validation; travel up to 25%.
System Verilog, Cadence Tools, Synopsys Tools, VCS, SpyGlass, Design Compiler, PrimeTime, Lab equipment
2mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in EE/CE required, 1+ year digital design experience, RTL coding in Verilog/SystemVerilog, UVM-based verification, Python/Perl scripting, STA/DFT experience, ASIC integration, pre/post-silicon validation, and C/C++ reference model work.
Verilog, SystemVerilog, UVM, Python, Perl, C, C++, Static Timing Analysis (STA), DFT
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