2mo
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Sr ProServe Account Executive , NAMER RTL/CPG
Arlington or Chicago or Dallas
$143k-$193k/yr OnsiteFull Time
5+ YOE5+ years technology sales or account management; target-driven; cloud/IT strategy experience.
CRM
2mo
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Programmable Logic Design Engineer
Germantown or Carlsbad or Independence or Englewood
$156k-$246k/yr OnsiteContract
5+ YOEBachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.
System Verilog, Verilog, VHDL, Xilinx Vivado, RTL design, FPGA design, Testbench development, Simulation
3mo
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Circuit Design Engineer
Annapolis Junction or Catonsville
$99k-$225k/yr OnsiteFull Time
10+ YOETen+ years ASIC design experience; TS/SCI with poly; BS in EE/SE/CE/CS or MS with relevant experience; RTL, FPGA, Python/Verilog/C/C++, etc.
Python, Verilog, C, C++, Bash, Java, RTL, FPGAs
2mo
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FPGA Engineer (VA, Reston )
Reston, Virginia, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm
1mo
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Digital Design Engineer - Level 5 - Linthicum
Linthicum, Maryland, United States
$186k-$279k/yr OnsiteFull Time
7+ YOEDegree in EE/CE/CS (Bachelor’s+12yr or Master’s+10yr or PhD+7yr), FPGA/ASIC/HDL (Verilog, VHDL) experience, FPGA IDEs (Xilinx, Microsemi), test/verification and RTL debug, mentoring skills, U.S. citizenship and ability to obtain Top Secret clearance.
Xilinx, Microsemi, HDL, Verilog, VHDL, RTL
1mo
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FPGA Developer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOEU.S. citizen able to obtain security clearance. 5+ years RTL FPGA design (VHDL/Verilog/SystemVerilog), FPGA implementation of image/signal processing, experience with Xilinx devices, high-speed interfaces, MATLAB/Python/C++, Vitis HLS/AI, and Linux driver development.
VHDL, Verilog, SystemVerilog, RTL, FPGA, Kintex, Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, MATLAB, Python, C++, Vitis HLS, Vitis AI, Linux
4w
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Engineer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOE5+ years RTL FPGA design experience (VHDL/Verilog/SystemVerilog), experience implementing image/signal processing on FPGAs, Xilinx device experience, PCIe/CoaXPress/10GbE/DDR interfaces, MATLAB/Python/C++, Vitis HLS/AI, Linux driver experience, U.S. citizenship and ability to obtain clearance.
VHDL, Verilog, SystemVerilog, RTL, Xilinx Kintex, Xilinx Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, Vitis HLS, Vitis AI, MATLAB, Python, C++, Linux
15h
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Lead ASIC Digital Design Engineer
Annapolis Junction or Telework or Boise or Salt Lake City or Bloomington
$177k-$187k/yr RemoteFull Time
8+ YOE8+ years ASIC/FPGA RTL design experience, ASIC tape-out and timing-closure experience, familiarity with FinFET nodes and commercial foundry flows, EDA tool and JIRA proficiency, strong RTL and microarchitecture skills.
JIRA, Microsoft Office
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
4w
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Senior FPGA Engineer
Fairfax, Virginia, United States
$76k-$141k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Xilinx, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, Versal AI Engines, Vivado Design Suite, Vivado IP Integrator, Vivado HW Debugger, Chipscope, SmartDebug, Libero, Git, Modelsim, Questasim, Aldec, UVVM, UVM, OVM, VHDL, SystemVerilog, MATLAB, Simulink, Linux, C, C++
3w
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA design experience, strong Verilog/VHDL and Xilinx Vivado skills, RFSoC/Versal experience, RTL simulation and hardware debug experience, U.S. citizenship and Secret clearance (or ability to obtain).
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Integrated Logic Analyzer (ILA), VIO, JTAG, ADRV9009, AD9081, JESD204B/C, Ethernet, PCIe, Aurora, AXI-Lite, AXI-Stream, DMA, Tcl, Python
5d
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FPGA Verification Engineer Level 3/4 - Linthicum
Linthicum Heights, Maryland, United States
$120k-$179k/yr OnsiteFull Time
5+ YOEU.S. citizen with 3–8+ years FPGA/RTL verification experience, proficiency with VUnit and HDL (SystemVerilog/Verilog/VHDL), ability to obtain DoD Secret/Top-Secret clearance, and degree in EE/CE/CS or related field.
VUnit, SystemVerilog, Verilog, VHDL, Synopsys, Mentor Graphics, Bash, Perl, Python, Tcl, Makefile, Xilinx, MicroChip
1mo
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
1mo
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Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado/Xilinx toolchains, Python/C++, MATLAB, Linux, Agile tools (Jira, Confluence); ability to obtain TS/SCI clearance; bachelor’s in EE or CE required.
Python, C++, MATLAB, Jira, Confluence, Verilog, VHDL, SystemVerilog, HLS, Vitis HLS, Vitis, Vivado, Tcl, Linux, UNIX, AXI-Stream, AXI-Lite, DMA, RTL, SDR, SOSA, VPX, GPU, Logic Analyzer, Oscilloscope, Spectrum Analyzer
1d
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Engineering and Physical Sciences Researcher- Mid to Experienced Level (Maryland)
Fort Meade, Maryland, United States
$105k-$193k/yr OnsiteFull Time
3+ YOEDegree in engineering, physics/astronomy, or related technical field; relevant research or engineering experience; publication and collaboration record; demonstrated technical skills in device/ASIC/architecture research.
Verilog, RTL, FPGA, Cadence, Synopsys
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