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RTL Design Manager
San Jose, California, United States
$200k-$300k/yr OnsiteFull Time
Lead a front-end RTL engineering team; strong RTL design, verification guidance, and automation experience; familiarity with Arm architecture, APB/AXI/CHI protocols, scripting (Perl/Python/Tcl); Bachelors or Masters in computer/electrical engineering.
PERL, Python, Tcl, LINT, CDC, UPF, Arm, APB, AXI, CHI, RTL
3mo
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SR RTL DESIGN
Boise, Idaho, United States
HybridFull Time
4+ YOEMaster’s or Bachelor’s in Electrical Engineering with 4+ or 5+ years pre-silicon RTL/ASIC design; Verilog/SystemVerilog; UPF; CDC/RDC; Synthesis and STA; RTL-to-GDS flows.
Verilog, SystemVerilog, UPF, CDC, RDC, Synthesis, STA
3w
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
3mo
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Staff RTL Engineer
Orlando, Florida, United States
OnsiteFull Time
7+ YOEStaff RTL Engineer with FPGA/RTL design, SystemVerilog, modelling, simulation, verification, integration and test; derive FPGA requirements from system; perform RTL design and testing.
SystemVerilog, Verilog, Python, FPGA design tools, HDL synthesis, VCS, Synplicity
1mo
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Senior RTL Design Engineer (123652)
United States
OnsiteFull Time
2+ YOE2+ years experience required in RTL coding (Verilog/SystemVerilog/VHDL), FPGA design (Xilinx/Altera), Vivado/Quartus, RTL synthesis, CDC/linting, lab debug; scripting experience preferred.
Verilog, SystemVerilog, VHDL, Xilinx, Altera, Vivado, Quartus, CDC, Linting, RTL Synthesis, ASIC, SoC
2mo
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PHY RTL Design Engineer
Irvine or San Diego or Sunnyvale
OnsiteFull Time
Bachelor's degree; DSP fundamentals; Digital communications; Proficiency in RTL design.
RTL Design, MATLAB, Verilog, UVM, DV, FPGA, Emulation, Power analysis, Synthesis
1mo
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HBM Sr RTL Engineer
Richardson, Texas, United States
OnsiteFull Time
1+ YOEHands-on RTL design and SoC integration experience with SystemVerilog/Verilog, RTL-to-GDS flow knowledge, scripting (Python/TCL/Perl/Shell), and 1+ years related experience; BS/MS in EE/CE preferred.
SystemVerilog, Verilog, Python, TCL, Perl, Shell
1mo
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RTL Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
8+ YOE8+ years VLSI/RTL design experience with System Verilog/Verilog, Python RTL generators, HLS, SoC integration, UPF low-power flow, synthesis/timing closure, linting and CDC/RDC checks, and emulation on Zebu/HAPS.
System Verilog, Verilog, Python, High-Level Synthesis (HLS), Zebu, HAPS, Unified Power Format (UPF)
1mo
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PCIe Subsystem RTL lead
San Jose or Bangalore
OnsiteFull Time
10+ YOE10+ years digital IC design with PCIe subsystem experience; hands-on RTL; sysverilog; PCIe bring-up; multi-clock domains.
SystemVerilog, Verilog, PCIe, UVM, RTL design, Synthesis and timing, PNR/Physical Design, debug instrumentation
3mo
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RTL Design Engineer
Austin or Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 2+ years experience; knowledge of RTL design, Verilog/SystemVerilog, and basic digital design.
Verilog, SystemVerilog, VHDL, Design Compiler, Genus, Python, Perl, TCL, ModelSim, VCS, Xcelium, UVM, OVM
1mo
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
2mo
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Processor ASIC RTL Design Engineer
San Diego, California, United States
$127k-$191k/yr OnsiteFull Time
2+ YOE2+ years RTL and microprocessor design experience; strong RTL design in System Verilog/Verilog, familiarity with linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC, and low-power techniques; BS/MS/PhD in EE/CS/CE or related.
System Verilog, Verilog, RTL, GDS2, linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC
3w
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
4d
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TPU RTL Design Engineer
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design experience focused on clocking/reset/timing-critical RTL,SystemVerilog and scripting (Python/Tcl/Perl) proficiency,experience with clock control and verification.
SystemVerilog, Python, Tcl, Perl
3mo
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Senior RTL Engineer/Lead
Austin, Texas, United States
$152k-$255k/yr OnsiteFull Time
8+ YOE8+ years RTL design experience for complex IP/CPU subsystems, strong SystemVerilog/Verilog and synthesis skills, front-end quality flow knowledge, scripting (Perl/Python/Tcl), and collaboration with DV/DFT/PD teams.
SystemVerilog, Verilog, Perl, Python, Tcl, Lint, CDC, LEC
1w
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RTL Design Engineer
North Reading, Massachusetts, United States
$123k-$197k/yr OnsiteFull Time
5+ YOEBSEE or MSEE in electrical engineering (or related) with 5+ years experience; extensive Verilog RTL design, logic synthesis, CDC/STA knowledge; Python/Tcl/Make scripting; experience with high-speed memory and serial interfaces.
Verilog, Python, Tcl, Make, Static Timing Analysis (STA)
4w
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Principal RTL Methodology Architect
Austin, Texas, United States
HybridFull Time
10+ YOEBS/MS in EE/CS or similar with 10+ years experience; deep RTL/SystemVerilog/Verilog expertise; experience with RTL methodology, IP reuse, linting and static analysis (SpyGlass, VC Lint), frontend EDA flows, Python and CI/CD; strong communication.
SystemVerilog, Verilog, SpyGlass, Synopsys VC SpyGlass, VC Lint, VCS, Xcelium, Questa, Python, CI/CD, UPF
2mo
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
1mo
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
4w
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Principal RTL Methodology Architect (767547)
Austin, Texas, United States
HybridFull Time
10+ YOE10+ years experience with SystemVerilog/Verilog RTL design, RTL methodology and signoff (lint, CDC, static analysis), EDA simulators, IP reuse, UPF low-power flows, Python automation and CI/CD; BS/MS in EE/CS.
SystemVerilog, Verilog, SpyGlass, Synopsys VC SpyGlass, VC Lint, VCS, Xcelium, Questa, Python, CI/CD, UPF, CDC
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