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HBM SoC RTL Design Engineer
Folsom, California, United States
$121k-$247k/yr OnsiteFull Time
3+ YOE3+ years SoC/RTL design experience, proficiency in SystemVerilog/Verilog, RTL-to-GDS flow knowledge, familiarity with EDA toolchains, scripting (Python/TCL/Perl/shell), and SoC integration skills.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell, Palladium, Veloce, Zebu
2mo
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HBM SoC RTL Design Engineer
Folsom, California, United States
$146k-$297k/yr OnsiteFull Time
10+ YOE10+ years in electrical/computer engineering; SystemVerilog/Verilog; RTL-to-GDS flow; Cadence/Synopsys/Siemens; Python/TCL/Perl scripting.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl
2mo
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Director, HBM RTL Design and Integration
Richardson or Folsom
$177k-$348k/yr OnsiteFull Time
15+ YOELead large-scale SoC RTL design and integration for HBM, manage cross-functional teams, and drive RTL-to-GDS flows with 15+ years of experience.
SystemVerilog, Python, TCL
2mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
2mo
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SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)
Richardson or Folsom
$177k-$334k/yr OnsiteFull Time
15+ YOEBachelors or Masters in electrical/computer engineering; 15+ years in related field; SystemVerilog/Verilog; RTL-to-GDS flow; Cadence/Synopsys/Siemens; Python/TCL/Perl.
SystemVerilog, Verilog, RTL, EDA tools (Cadence, Synopsys, Siemens), Python, TCL, Perl
1mo
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
1mo
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Director, Custom HBM Design and Architecture
Richardson or Folsom
$199k-$379k/yr OnsiteFull Time
15+ YOEProven SoC design leadership with deep RTL and RTL-to-GDS expertise, SoC integration, pre/post-silicon validation, familiarity with EDA tools and scripting (SystemVerilog, Python, TCL), and knowledge of DRAM/HBM systems.
SystemVerilog, Python, TCL, EDA tools, hardware emulation
2mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
2mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
1w
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Principal Engineer, SOC Design
Folsom, California, United States
$199k-$319k/yr OnsiteFull Time
15+ YOEExtensive SoC architecture and RTL development experience with modern DRAM technologies, verification/debugging skills, FPGA prototyping or silicon bring-up experience, and strong technical leadership.
SystemVerilog, Verilog, FPGA
1mo
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HBM Hardware Emulation Architect
Folsom or Richardson
$146k-$309k/yr OnsiteFull Time
10+ YOEBachelor's/Master's in EE/CE or equivalent, 10+ years engineering/design experience, strong RTL design and debug, hands-on hardware emulation platform experience, SoC architecture and firmware interaction expertise.
Palladium, Veloce, Zebu, FPGA
1mo
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Principal DFT Engineer, HBM
Folsom, California, United States
$146k-$309k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE or related, 7+ years SoC/DFT experience, proficiency with scan/MBIST/LBIST/JTAG/ATPG, RTL-to-GDS flows, EDA tools (Siemens, Synopsys, Cadence), and scripting (Python, Tcl, Perl).
Siemens, Synopsys, Cadence, Python, Tcl, Perl
2mo
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Mixed Signal Logic Design Engineer
Folsom or San Jose or Santa Clara
$122k-$232k/yr OnsiteFull Time
4+ YOEBachelor's with 4+ years or Master's with 3+ years or PhD with 1+ year in CS/CE/EE; 2+ years RTL design SystemVerilog/Verilog; mixed-signal, UPF, clock gating; VCS/Verdi; FE tools; no visa sponsorship.
SystemVerilog, Verilog, VCS, Verdi, UPF, Lint, CDC, RDC, Synthesis, Voltage Domain Crossings, DDR, LPDDR, VSCode, Git
3w
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GPU Performance Architect
Folsom or Santa Clara
$127k-$217k/yr HybridFull Time
Develop performance models and prototypes for GPU/SoC systems; analyze ML/HPC workloads; write and optimize GPU kernels; strong programming in C/C++/Python; knowledge of CUDA/OpenCL and ML frameworks.
TensorFlow, PyTorch, CUDA, OpenCL, C, C++, Python, Hip, Triton, MLIR, LLVM, RTL, System C