5 rtl design engineer jobs at 3 companies in Chicago, IL
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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
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Senior FPGA Engineer
Chicago or New York City or London or United States or Canada or Europe or Asia
OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering, 3+ years FPGA/hardware experience, Verilog/System Verilog and RTL skills, FPGA design flow (synthesis, place & route, static timing), SoC and TCP/IP knowledge, lab debugging, EM/board characterization.
Verilog, System Verilog, RTL, TCP/IP, XILINX, ALTERA
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Hardware Engineer
Chicago, Illinois, United States
$200k-$225k/yr OnsiteFull Time
BS in EE/CE/CS or related, strong RTL design using SystemVerilog, C++ experience, verification and multi-clock-domain knowledge, Ethernet fundamentals, Python/Bash scripting, and strong debugging and collaboration skills.
SystemVerilog, C++, Python, Bash, FPGA, PMA (Physical Media Attachment), Ethernet, RTL
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FPGA Engineer (IL, Schaumburg)
Schaumburg, Illinois, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, C/C++, Python, VHDL/Verilog; hardware security; FPGA design and verification; system integration; cryptography concepts.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, Versal, Agilex, AXI, Avalon, cocotb, pyuvm
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Junior FPGA Developer
Chicago, Illinois, United States
$100k-$175k/yr OnsiteFull Time
BS/MS in EE/CE or related field, hands-on RTL design in Verilog/SystemVerilog, familiarity with ModelSim/QuestaSim/Vivado/Quartus and synthesis flow, Linux proficiency, Python/C/C++ a plus, eagerness to apply AI tools and learn HFT.
Verilog, SystemVerilog, ModelSim, QuestaSim, Vivado, Quartus, Linux, Python, C, C++