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RTL Design Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with RTL design and Verilog/SystemVerilog preferred.
Verilog, SystemVerilog, Python, Perl
2w
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
1mo
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RTL Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
8+ YOE8+ years VLSI/RTL design experience with System Verilog/Verilog, Python RTL generators, HLS, SoC integration, UPF low-power flow, synthesis/timing closure, linting and CDC/RDC checks, and emulation on Zebu/HAPS.
System Verilog, Verilog, Python, High-Level Synthesis (HLS), Zebu, HAPS, Unified Power Format (UPF)
3w
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
1mo
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Senior RTL Design Engineer (123652)
United States
OnsiteFull Time
2+ YOE2+ years experience required in RTL coding (Verilog/SystemVerilog/VHDL), FPGA design (Xilinx/Altera), Vivado/Quartus, RTL synthesis, CDC/linting, lab debug; scripting experience preferred.
Verilog, SystemVerilog, VHDL, Xilinx, Altera, Vivado, Quartus, CDC, Linting, RTL Synthesis, ASIC, SoC
3mo
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RTL Design Engineer
Austin or Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 2+ years experience; knowledge of RTL design, Verilog/SystemVerilog, and basic digital design.
Verilog, SystemVerilog, VHDL, Design Compiler, Genus, Python, Perl, TCL, ModelSim, VCS, Xcelium, UVM, OVM
4d
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TPU RTL Design Engineer
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design experience focused on clocking/reset/timing-critical RTL,SystemVerilog and scripting (Python/Tcl/Perl) proficiency,experience with clock control and verification.
SystemVerilog, Python, Tcl, Perl
1mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
2mo
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Processor ASIC RTL Design Engineer
San Diego, California, United States
$127k-$191k/yr OnsiteFull Time
2+ YOE2+ years RTL and microprocessor design experience; strong RTL design in System Verilog/Verilog, familiarity with linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC, and low-power techniques; BS/MS/PhD in EE/CS/CE or related.
System Verilog, Verilog, RTL, GDS2, linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC
3w
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RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
3mo
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Senior RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$159k-$194k/yr OnsiteFull Time
3+ YOE3+ years of RTL design experience; Verilog/SystemVerilog/VHDL; CPU RTL design; Chisel/Scala experience a plus; strong software engineering skills.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, Jira, Confluence
3mo
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RTL Design / Microarchitecture Engineer
Sunnyvale, California, United States
$160k-$220k/yr OnsiteFull Time
5+ YOE5–10 years of RTL design and microarchitecture experience; strong SystemVerilog/Verilog expertise; ASIC/SoC development experience.
SystemVerilog, Verilog, Synopsys VCS, Cadence Xcelium, Synopsys Design Compiler, Scripting (Python/TCL)
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
3d
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
1mo
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SR RTL DESIGN
Boise, Idaho, United States
OnsiteFull Time
4+ YOEMaster's in EE +4 yrs or Bachelor's in EE +5 yrs; proficiency in Verilog/SystemVerilog, RTL design and low-power methodologies (UPF, CDC/RDC), synthesis, STA, and RTL simulation; strong collaboration and PPA focus.
Verilog, SystemVerilog, UPF, CDC, RDC, RTL-to-GDS, lint, synthesis, logic synthesis, RTL simulation tools, static timing analysis
3mo
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PRINICPAL RTL DESIGN
Boise, Idaho, United States
HybridFull Time
8+ YOELead RTL design of DRAM IP; requires advanced degree with 8+ years or 10+ years pre-silicon RTL experience; strong Verilog/SystemVerilog; low-power design; RTL signoff.
Verilog, SystemVerilog, UPF, CDC, RDC, Synthesis, Static Timing Analysis, Verification Tools
2mo
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Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
2mo
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
3mo
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ASIC RTL Design Engineer (784246)
Austin, Texas, United States
HybridFull Time
3+ YOEBS in Electrical or Computer Engineering; several years of hands-on RTL design experience; strong digital logic; proficient in C/C++, TCL, Python; SystemVerilog/Verilog/VHDL; CDC/STA knowledge; RTL linting/CDC tools; AMBA experience; EDA tool familiarity; Git/Linux.
SystemVerilog, Verilog, VHDL, C, C++, Python, TCL, EDA tools, SpyGlass, AMBA, Cadence, Mentor, Synopsys, Git, Linux
2mo
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Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
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