20 rtl design engineer jobs at 9 companies in Coolidge, AZ
1mo
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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
4d
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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
2w
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Staff Digital Design Engineer
Chandler, Arizona, United States
HybridFull Time
11+ YOE>10 years digital design experience, degree in EE/CE/CS or related, fluent Verilog/SystemVerilog, ASIC methodology knowledge, Lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, travel readiness.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
1mo
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Staff Digital Design Engineer (AI/ML)
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEMS (EE/CE) with 7+ years or PhD with 5+ years (BSEE/BSCE considered); strong Verilog/SystemVerilog RTL and tape-out experience; Python/Tcl/shell scripting; Cadence Genus/Innovus/Tempus/Conformal; synthesis, STA, DFT knowledge.
Verilog, SystemVerilog, Python, Tcl, Shell, Genus, Innovus, Tempus, Conformal
1w
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Senior Engineer I- Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEBSEE with 5+ years experience, proficiency in Verilog/SystemVerilog and UVM, Python and TCL scripting, familiarity with Synopsys/Cadence/Siemens EDA tools, and experience with RTL design and verification.
Verilog, SystemVerilog, UVM, Python, TCL, Shell, Synopsys, Cadence, Siemens, AI/ML
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
2mo
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FPGA Engineer (Space)
Tempe, Arizona, United States
$133k-$210k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical/Computer Engineering; 6+ years FPGA design; SystemVerilog/VHDL; RTL design; lab/test experience; US citizenship; travel up to 10%
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Quartus, Synplify, MATLAB
3w
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Digital Physical Design (P&R) Intern
Chandler, Arizona, United States
OnsiteFull Time
Pursuing MSEE with digital design coursework, knowledge of digital backend flow from synthesis to GDS2, willing to relocate to Phoenix metro and work minimum 3 days/week onsite; strong problem-solving and teamwork skills; prior flow experience a plus.
Cadence, GDS2, RTL, Synthesis
3mo
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FPGA Engineer (AZ, Phoenix)
Phoenix, Arizona, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and hardware security systems; RTL, C/C++, Python, VHDL/Verilog; FPGA tools; security clearance.
VHDL, Verilog, SystemVerilog, Python, C, C++, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, AcE, AXI, Avalon
1d
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Systems and Test Integration Engineer - FPGA Integration & Verification
Scottsdale, Arizona, United States
$91k-$101k/yr OnsiteFull Time
2+ YOEBachelor's in systems/engineering/math plus 2+ years (or Master's plus 6 months), TS/SCI clearance obtainable, FPGA design and hardware bring-up experience, RTL (SystemVerilog/VHDL), scripting (Python,Tcl), Linux and Git proficiency.
SystemVerilog, VHDL, Xilinx/AMD Vivado, Lattice Diamond, Radiant, Python, Tcl, Git, GitLab CI, RHEL, Ubuntu, Linux shell scripts, JTAG, oscilloscope, protocol analyzer
6d
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Hardware Designer
Phoenix or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelors in Electrical/Computer Engineering, high-speed PCB and system design expertise, familiarity with FPGA and signal integrity, bench bring-up and test experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test set, signal analyzer, oscilloscope, VNA, signal generator