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44 rtl design engineer jobs at 8 companies in Plano, TX

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RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
IC Enable
IC Enable: Specialized design and layout services for integrated circuits.
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
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HBM SoC RTL Design Engineer
Folsom or Richardson
$146k-$297k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
10+ YOEBachelor's or master's in EE/CE (required) with 10+ years' experience; proficiency in SystemVerilog/Verilog, SoC integration, RTL-to-GDS flow, EDA tools (Cadence/Synopsys/Siemens), and scripting (Python, TCL, Perl, shell).
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, Shell, Palladium, Veloce, Zebu
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Director, HBM RTL Design and Integration
Richardson or Folsom
$177k-$348k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
15+ YOELead large-scale SoC RTL design and integration for HBM, manage cross-functional teams, and drive RTL-to-GDS flows with 15+ years of experience.
SystemVerilog, Python, TCL
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Senior Engineer, Digital Design Engineering
Dallas, Texas, United States
$124k-$175k/yr HybridFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
2+ YOEMaster’s degree in Electrical/Electronic Engineering or Computer Science/Engineering; 2+ years in digital design or related; RTL design, verification, and CAD tools experience.
Verilog, SystemVerilog, Cadence, Synopsys, RTL, Synthesis, Simulation, Lint, CDC
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
ams OSRAM
ams OSRAMSIX Swiss Exchange: AMS: Develops and manufactures intelligent sensors and optical solutions.
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
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Digital IC Design Engineer | Custom
Dallas, Texas, United States
OnsiteFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
8+ YOEBachelor's in EE/ECE/Computer Engineering, 8 years engineering experience including 3 years mixed-signal design verification, experience with Gates+SDF timing verification, automation scripting, and mixed-signal verification flows.
JasperGold, Gates+SDF, RTL, STA
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
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Senior ASIC/FPGA Design Engineer
McKinney, Texas, United States
$87k-$165k/yr OnsiteFull Time
RTX
RTXNYSE: RTX: RTX provides advanced aerospace and defense systems and services.
5+ YOEBachelor's in STEM,5+ years FPGA/ASIC design and RTL experience,experience with Xilinx/Altera and high-speed interfaces,Python/Perl/Shell scripting,ability to obtain U.S. government security clearance;U.S. citizenship required.
Xilinx, Altera, Python, Perl, Shell, System Verilog, UVM, MATLAB, PCI/PCIe, VPX, Gb Ethernet, Ienterlaken
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Director, Design Management
Richardson, Texas, United States
$191k-$332k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Manufacturer of semiconductors and provider of wafer fabrication services.
Proven track record delivering SoC programs, expertise across RTL/DV/DFT/Physical Design, program and cost modeling, SOW and contractor management, strong leadership and communication.
RTL, DV, DFT, Physical Design, EDA
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
Infineon Technologies
Infineon TechnologiesFrankfurt Stock Exchange: IFX: Designs and manufactures semiconductors for power and IoT systems.
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
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Director, Design Management
Richardson, Texas, United States
$191k-$332k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Semiconductor foundry providing chip design and fabrication services.
Proven track record delivering complex SoC programs, expertise across RTL/DV/DFT/Physical Design, experience in cost/resource modeling, SOW and contractor management, customer-facing feasibility work, and leadership of global teams.
RTL, DV, DFT, Physical Design, EDA
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