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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
1mo
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Senior CPU RTL Design Engineer – Power Management
Austin or Phoenix
$164k-$269k/yr HybridFull Time
7+ YOEBachelor's (9+ years) or Master's (7+ years) in ECE/CE/CS. Experience in low-power CPU/SoC RTL design, power management (DVFS, power states), RTL development (Verilog/SystemVerilog), debug and system-level design. Preferred: CDC, static timing analysis, UPF, lint.
SystemVerilog, Verilog, x86 assembly, CDC, UPF, static timing analysis, lint
3w
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Physical Design Engineer
Beaver Brook or Phoenix
$122k-$200k/yr OnsiteFull Time
2+ YOEExperience implementing physical design flows for custom IP/SoC, proficiency with EDA tools, RTL/GDS knowledge, scripting (TCL), and 2+ years of relevant experience with a relevant degree.
industry-standard EDA tools, TCL, RTL, GDS
3w
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Physical Design Engineer
Massachusetts or Phoenix
$91k-$149k/yr OnsiteFull Time
0+ YOEDesign and implement physical IC/SoC from RTL to GDS, perform synthesis/place-and-route/CTS/STA, power and noise analysis, verification and optimization using EDA tools.
EDA tools, TCL
2w
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Staff Digital Design Engineer
Chandler, Arizona, United States
HybridFull Time
11+ YOE>10 years digital design experience, degree in EE/CE/CS or related, fluent Verilog/SystemVerilog, ASIC methodology knowledge, Lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, travel readiness.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
1w
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Sr. Logic Design Engineer
Santa Clara or Phoenix or Hillsboro
$142k-$200k/yr HybridFull Time
4+ YOEBachelor's in Electrical/Computer Engineering with 4+ years (or Master's w/2+, PhD w/1+) and experience in RTL/System Verilog, front-end lint/synthesis tools, VCS/Verdi, UPF, CDC and IP environment.
System Verilog, VCS, Verdi, UPF, Lint, Synthesis
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Mixed Signal Logic Design Engineer
Hillsboro or Santa Clara or Phoenix
$142k-$200k/yr OnsiteFull Time
3+ YOEBS/MS in EE/CE with 3+ years' experience, SystemVerilog, mixed-signal and high-speed I/O knowledge, experience with multi-clock designs, RTL quality and CDC tools, scripting (Perl/bash/Python) preferred.
SystemVerilog, Perl, bash, csh, Python, AMS simulation tools, linting, CDC analysis, AI tools, UCIe, PCIe, USB
1mo
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Staff Digital Design Engineer (AI/ML)
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEMS (EE/CE) with 7+ years or PhD with 5+ years (BSEE/BSCE considered); strong Verilog/SystemVerilog RTL and tape-out experience; Python/Tcl/shell scripting; Cadence Genus/Innovus/Tempus/Conformal; synthesis, STA, DFT knowledge.
Verilog, SystemVerilog, Python, Tcl, Shell, Genus, Innovus, Tempus, Conformal
3mo
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Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
1w
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Senior Engineer I- Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEBSEE with 5+ years experience, proficiency in Verilog/SystemVerilog and UVM, Python and TCL scripting, familiarity with Synopsys/Cadence/Siemens EDA tools, and experience with RTL design and verification.
Verilog, SystemVerilog, UVM, Python, TCL, Shell, Synopsys, Cadence, Siemens, AI/ML
2mo
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Principal Engineer - Digital Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelors with 10+ years in digital design; RTL coding/verification; USB/Ethernet PHY knowledge; Verilog/SystemVerilog; UVM/VMM a plus; ASIC flow; CAD tools; timing; scripting.
Verilog, SystemVerilog, UVM, Questa, Design Compiler, Formality, Spyglass, Crossing Clock domain checking, lint, stuck-at, At-Speed scan, Scripting (C, TCL, Perl, Awk, UNIX shell), CVS, Perforce, DesignSync
1w
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT
1mo
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
2mo
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FPGA Engineer (Space)
Tempe, Arizona, United States
$133k-$210k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical/Computer Engineering; 6+ years FPGA design; SystemVerilog/VHDL; RTL design; lab/test experience; US citizenship; travel up to 10%
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Quartus, Synplify, MATLAB
2w
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Digital Physical Design (P&R) Intern
Chandler, Arizona, United States
OnsiteFull Time
Pursuing MSEE with digital design coursework, knowledge of digital backend flow from synthesis to GDS2, willing to relocate to Phoenix metro and work minimum 3 days/week onsite; strong problem-solving and teamwork skills; prior flow experience a plus.
Cadence, GDS2, RTL, Synthesis
3w
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Senior DfT Engineer
Chandler, Arizona, United States
HybridFull Time
3+ YOEMaster's (MSEE) in relevant fields, 3+ years DfT/digital design experience, strong RTL coding and verification skills, Verilog/SystemVerilog proficiency, problem solving and communication skills.
Verilog, SystemVerilog
2mo
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FPGA Engineer (AZ, Phoenix)
Phoenix, Arizona, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and hardware security systems; RTL, C/C++, Python, VHDL/Verilog; FPGA tools; security clearance.
VHDL, Verilog, SystemVerilog, Python, C, C++, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, AcE, AXI, Avalon
3w
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Senior Digital Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years digital design experience, degree in electrical/computer discipline, fluent Verilog/SystemVerilog, ASIC methodology, lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, willing to travel.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
4d
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Hardware Designer
Phoenix or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelors in Electrical/Computer Engineering, high-speed PCB and system design expertise, familiarity with FPGA and signal integrity, bench bring-up and test experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test set, signal analyzer, oscilloscope, VNA, signal generator
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