40 rtl design jobs at 12 companies in Portland, OR
3mo
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Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
1w
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Senior CPU RTL Design Engineer
Austin or Hillsboro
$164k-$312k/yr OnsiteFull Time
6+ YOEBachelor's degree with 8+ years, master's with 7+ years, or PhD with 4+ years; 6+ years CPU microarchitecture and logic design; technical leadership, timing closure, power convergence, and CPU execution experience.
RTL, AI
3mo
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Senior Engineer, Digital Design Engineering
Beaverton, Oregon, United States
$122k-$174k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2 years of digital design/verification experience; proficiency with RTL, Verilog/SystemVerilog, and CAD tools; knowledge of verification methods and test benches.
Verilog, SystemVerilog, Cadence, Synopsys, RTL design, Test benches, ASIC design flow
1mo
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$136k-$265k/yr OnsiteFull Time
5+ YOEMasters in Computer or Electrical Engineering or equivalent,5+ years chip/SOC design experience,RTL/verification and design automation expertise,proficient in scripting (Perl/Python),strong analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
2d
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CPU Design Methodology Engineer
Hillsboro or Austin or Arizona or Santa Clara
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's in computer or electrical engineering or equivalent experience; 8+ years in chip design focused on SoC integration and design automation; RTL, verification, scripting, synthesis, and physical design experience.
Verilog, Universal Verification Methodology (UVM), SystemVerilog, Perl, Python
6h
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
3w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with 8+ years ASIC/SoC design experience; RTL-to-silicon expertise, Synopsys/Cadence tool experience, Verilog/SV and scripting languages, strong communication and problem-solving skills.
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
2w
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
2w
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
3w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,experience with Synopsys and Cadence tools,proficiency in Verilog,SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
3w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with VLSI focus,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,knowledge of Synopsys and Cadence flows,proficiency in Verilog/SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, Subversion, git, GitHub, FPGA, AI Copilot (LLM-based tools)
5d
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
1+ YOERequires a relevant engineering or computer science degree and 1–5+ years of technical engineering experience; preferred experience includes semiconductor physical design, tape-outs, low-power methods, and signoff workflows.
synthesis, place-and-route, clock construction, CTS, RTL, DFT, RTL to GDS, EMIR, formal equivalence, low-power verification
1mo
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Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin or San Jose
$123k-$197k/yr OnsiteFull Time
3+ YOEBachelor's (5+ yrs) or Master's (3+ yrs) in EE or related, experience with FPGA RTL, timing closure, simulation, DRAM/Flash interfaces, Verilog, C/C++, and lab validation.
Verilog HDL, C, C++, Altera/AMD FPGA tool flows, UVM, Linux, Windows
2mo
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FE RTL Infrastructure - CAD Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Design and build infrastructure for high-performance, power-efficient processors and system-on-chip technology; collaborate within silicon and manufacturing teams.
1mo
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Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
1w
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CPU Emulation Engineer, Silicon
Austin or Mountain View or Portland or Poughkeepsie
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent practical experience; 8 years with emulation or FPGA platforms; RTL design using Verilog or SystemVerilog; scripting with Python, Perl, TCL, or Makefiles.
Synopsys ZeBu, HAPS, Cadence Palladium, Protium, Siemens Veloce, Verilog, SystemVerilog, Python, Perl, TCL, Makefiles, Field-Programmable Gate Array (FPGA), Register-Transfer Level (RTL)
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