2w
Save
Mark Applied
Hide
RTL Design Manager
San Jose, California, United States
$200k-$300k/yr OnsiteFull Time
Lead a front-end RTL engineering team; strong RTL design, verification guidance, and automation experience; familiarity with Arm architecture, APB/AXI/CHI protocols, scripting (Perl/Python/Tcl); Bachelors or Masters in computer/electrical engineering.
PERL, Python, Tcl, LINT, CDC, UPF, Arm, APB, AXI, CHI, RTL
3mo
Save
Mark Applied
Hide
RTL Design Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design experience; Verilog/SystemVerilog; front-end tools; mixed-signal and analog concepts; scripting (Perl, JSON, Python); GenAI tooling for RTL design.
Verilog, SystemVerilog, Verilog simulators, UPF, Python, Perl, JSON
3mo
Save
Mark Applied
Hide
RTL Design Engineer
Austin or Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 2+ years experience; knowledge of RTL design, Verilog/SystemVerilog, and basic digital design.
Verilog, SystemVerilog, VHDL, Design Compiler, Genus, Python, Perl, TCL, ModelSim, VCS, Xcelium, UVM, OVM
3mo
Save
Mark Applied
Hide
PRINICPAL RTL DESIGN
Boise, Idaho, United States
HybridFull Time
8+ YOELead RTL design of DRAM IP; requires advanced degree with 8+ years or 10+ years pre-silicon RTL experience; strong Verilog/SystemVerilog; low-power design; RTL signoff.
Verilog, SystemVerilog, UPF, CDC, RDC, Synthesis, Static Timing Analysis, Verification Tools
1mo
Save
Mark Applied
Hide
SR RTL DESIGN
Boise, Idaho, United States
OnsiteFull Time
4+ YOEMaster's in EE +4 yrs or Bachelor's in EE +5 yrs; proficiency in Verilog/SystemVerilog, RTL design and low-power methodologies (UPF, CDC/RDC), synthesis, STA, and RTL simulation; strong collaboration and PPA focus.
Verilog, SystemVerilog, UPF, CDC, RDC, RTL-to-GDS, lint, synthesis, logic synthesis, RTL simulation tools, static timing analysis
1mo
Save
Mark Applied
Hide
Senior RTL Design Lead (110101)
United States
OnsiteFull Time
Advanced RTL design expertise with Verilog/VHDL, familiarity with Modelsim and Synopsys Design Compiler, verification experience with UVM/SystemVerilog, team leadership and mentorship skills; RTL certification is optional.
Verilog, VHDL, Modelsim, Synopsys Design Compiler, UVM, SystemVerilog
1mo
Save
Mark Applied
Hide
RTL Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
8+ YOE8+ years VLSI/RTL design experience with System Verilog/Verilog, Python RTL generators, HLS, SoC integration, UPF low-power flow, synthesis/timing closure, linting and CDC/RDC checks, and emulation on Zebu/HAPS.
System Verilog, Verilog, Python, High-Level Synthesis (HLS), Zebu, HAPS, Unified Power Format (UPF)
3w
Save
Mark Applied
Hide
RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
4d
Save
Mark Applied
Hide
TPU RTL Design Engineer
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design experience focused on clocking/reset/timing-critical RTL,SystemVerilog and scripting (Python/Tcl/Perl) proficiency,experience with clock control and verification.
SystemVerilog, Python, Tcl, Perl
2mo
Save
Mark Applied
Hide
Processor ASIC RTL Design Engineer
San Diego, California, United States
$127k-$191k/yr OnsiteFull Time
2+ YOE2+ years RTL and microprocessor design experience; strong RTL design in System Verilog/Verilog, familiarity with linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC, and low-power techniques; BS/MS/PhD in EE/CS/CE or related.
System Verilog, Verilog, RTL, GDS2, linting, CDC, LEC, CLP, synthesis, static timing analysis, PLDRC
1mo
Save
Mark Applied
Hide
SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
3mo
Save
Mark Applied
Hide
RTL Design / Microarchitecture Engineer
Sunnyvale, California, United States
$160k-$220k/yr OnsiteFull Time
5+ YOE5–10 years of RTL design and microarchitecture experience; strong SystemVerilog/Verilog expertise; ASIC/SoC development experience.
SystemVerilog, Verilog, Synopsys VCS, Cadence Xcelium, Synopsys Design Compiler, Scripting (Python/TCL)
2mo
Save
Mark Applied
Hide
Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
3d
Save
Mark Applied
Hide
Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
3w
Save
Mark Applied
Hide
RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
3mo
Save
Mark Applied
Hide
Senior RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$159k-$194k/yr OnsiteFull Time
3+ YOE3+ years of RTL design experience; Verilog/SystemVerilog/VHDL; CPU RTL design; Chisel/Scala experience a plus; strong software engineering skills.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, Jira, Confluence
3mo
Save
Mark Applied
Hide
ASIC RTL Design Engineer (784246)
Austin, Texas, United States
HybridFull Time
3+ YOEBS in Electrical or Computer Engineering; several years of hands-on RTL design experience; strong digital logic; proficient in C/C++, TCL, Python; SystemVerilog/Verilog/VHDL; CDC/STA knowledge; RTL linting/CDC tools; AMBA experience; EDA tool familiarity; Git/Linux.
SystemVerilog, Verilog, VHDL, C, C++, Python, TCL, EDA tools, SpyGlass, AMBA, Cadence, Mentor, Synopsys, Git, Linux
3mo
Save
Mark Applied
Hide
Senior Staff RTL Design Engineer- 16908
Boxborough, Massachusetts, United States
$138k-$208k/yr OnsiteFull Time
10+ YOE10+ years ASIC digital design experience with production RTL ownership, Verilog and Perl proficiency, knowledge of synthesis, timing analysis, and power optimization; Bachelor's degree in EE/CE or related field required.
Verilog, Perl
2mo
Save
Mark Applied
Hide
Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
2mo
Save
Mark Applied
Hide
Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
Explore Jobs