19 rtl engineer jobs at 10 companies in Acton, CA
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
2mo
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Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$125k-$195k/yr HybridFull Time
6+ YOEBachelor's in EE/CS (required). 6+ years FPGA design (or 4+ with MS, 2+ with PhD). Experience with fixed‑point DSP, multi‑clock FPGA designs, Xilinx FPGAs and Vivado. U.S. Person required; background check and drug test required.
Xilinx FPGAs, Vivado IDE, MATLAB, logic analyzers
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FPGA Design Engineer
Los Angeles or Irvine
$100k-$140k/yr HybridFull Time
6+ YOESenior FPGA design expert with 6+ years (MS: 4y; PhD: 2y) in fixed-point DSP, multiple clock-domain FPGA designs, Xilinx Vivado.
Xilinx FPGA, Vivado, MATLAB, HDL, FPGA design, RTL coding
3mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
1mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
1mo
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Sr. FPGA Engineer
El Segundo or Los Angeles or Hawthorne
$160k-$225k/yr OnsiteFull Time
5+ YOEB.S. in engineering or CS, 5+ years FPGA/RTL experience, Verilog/SystemVerilog, Vivado toolchain, AXI protocols, ARM/SoC FPGA experience, Python/Bash scripting, U.S. Person status required.
Verilog, SystemVerilog, ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream), Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP/UDP/IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins, NTP, PTP, Ettus, NI, HackRF, HLS Synthesis, GPU
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Static Timing Analysis (STA) Engineer – (Lead or Senior)
El Segundo, California, United States
$146k-$239k/yr OnsiteFull Time
5+ YOEBachelor's degree in a relevant technical field, 5+ years timing closure experience on ASICs/FPGAs, ASIC tape-out experience, RTL-to-GDS knowledge, and proficiency with timing, synthesis, and scripting tools.
Synopsys Primetime, Cadence Tempus, Synopsys Design Compiler, Cadence Genus, Vivado, Synopsys Fusion Compiler, Formality, Cadence LEC, TCM, Fishtail, Python, TCL, Perl, Unix shell, C SHELL, RTL, GDS, ASIC, FPGA
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
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Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
1w
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
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Senior FPGA Engineer
Long Beach, California, United States
$148k-$222k/yr OnsiteFull Time
5+ YOEBachelors in EE/Computer Eng or related; 5+ years FPGA development and high-speed digital systems experience in mission-critical applications; RTL/verification/synthesis/timing expertise; cross-functional collaboration skills.
VHDL, Verilog, SystemVerilog, SpinalHDL, Chisel, Vitis, SystemC, Simulink, RISC-V, AMD Xilinx, Intel, Microchip, CI/CD
6d
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
1mo
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
2mo
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Electrical Engineer II ASIC/FPGA Verification (Onsite)
El Segundo, California, United States
$76k-$144k/yr OnsiteFull Time
2+ YOEDegree in STEM and at least 2 years of relevant experience; active SECRET security clearance; RTL/VHDL/Verilog experience; testbench development; familiarity with ASIC/FPGA verification.
SystemVerilog, OVM/UVM, VHDL, Verilog, Questasim, Synplify, Quartus, Vivado, C++, Perl, Git, Subversion
2w
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Principal ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$118k-$225k/yr OnsiteFull Time
8+ YOEU.S. citizen with active transferable Secret clearance, STEM degree with 8+ years (or advanced degree with 5+ years), 4+ years RTL/SystemVerilog/VHDL/Verilog verification, testbench and coverage development, mentoring experience, and familiarity with Git/Subversion and simulation tools.
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, Unix/Linux, C, C++, Python, Perl, shell, QuestaSim, Synplify, Quartus, Vivado
1w
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$144k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEBS in EE/CE,7+ years digital design and SoC/FPGA experience,proficiency in SystemVerilog/Verilog,experience with SoC integration,timing knowledge,and simulation/debugging skills.
SystemVerilog, Verilog, Questasim, AXI, AHB, FPGA, SoC, RTL
3mo
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Manager, ASIC Design Engineering (Starshield Satellite Engineering)
Hawthorne, California, United States
$190k-$245k/yr OnsiteFull Time
5+ YOE2+ MgmtLead ASIC/FPGA design team; RTL/Verilog; 5+ years RTL/FPGA/ASIC; 2+ years management; Bachelor's in engineering.
Verilog, SystemVerilog, HDL simulators, VCS, Questa, IES, Spyglass, Xilinx Vivado, Altera Quartus II, Python, TCL, EDA tools
5d
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R&D Software Engineering Internship
Calabasas or Santa Clara
$40-$43/hr OnsiteInternship
Bachelor’s or Master’s in EE/CE or related, strong FPGA development experience (RTL, simulation, synthesis, debug), exposure to VHDL/Verilog/SystemVerilog, and strong analytical and communication skills.
VHDL, Verilog, SystemVerilog, PCIe, Ethernet, SerDes
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