928 rtl engineer jobs at 178 companies in United States
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RTL Design Engineer
Rochester, New York, United States
$145k-$217k/yr OnsiteFull Time
Bachelor's or master's in electrical or computer engineering; experience with SystemVerilog RTL, timing constraints, synthesis, lint, CDC/RDC, Python, TCL, mixed-signal integration, and post-silicon debug.
SystemVerilog, SDC, Python, TCL, Verilog-AMS, UPF, I²C, SPI, APB, SVID, PMBus, RTL, ECO
2mo
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
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RTL integration Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's plus 12+ years experience; deep RTL, UVM/SystemVerilog, synthesis, timing, CDC/RDC, GLS, SDF simulations, NCSim/VCS, Palladium modeling, STA, and strong debugging and communication skills.
RTL, UVM, SystemVerilog, SDF, NCSim, VCS, Palladium
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Senior RTL Engineer
Santa Clara, California, United States
$200k-$500k/yr OnsiteFull Time
8+ YOE8+ years RTL design experience for complex digital systems, expert Verilog/SystemVerilog, strong computer architecture and microarchitecture knowledge, tapeout ownership, memory and interconnect familiarity.
Verilog, SystemVerilog, AXI, CHI, ACE, LPDDR, DDR, HBM, FPGA
2w
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RTL Design Engineer
Richardson, Texas, United States
HybridFull Time
Bachelor’s or master’s degree in engineering; experienced Verilog/SystemVerilog RTL designer with ASIC/SoC flows, synthesis, verification debug, EDA tools, and cross-functional IC development experience.
Verilog, SystemVerilog, ASIC, SoC, Electronic Design Automation (EDA), CDC, APR
2mo
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
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RTL Design Engineer
Austin or Phoenix or Hillsboro
$91k-$173k/yr OnsiteFull Time
2+ YOEBachelor's degree with 2+ years of experience or master's degree in electrical/computer engineering; coursework or experience in logic design, microprocessors, architecture, RTL, Verilog/SystemVerilog or VHDL, synthesis tools, and scripting.
Verilog, SystemVerilog, VHDL, Design Compiler, Genus, Python, Perl, TCL, x86 assembly language
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Sr/Principal RTL Design Engineer
Sunnyvale or Bengaluru
OnsiteFull Time
Experienced RTL design engineer to implement RTL blocks and collaborate closely with architects and micro-architects.
1w
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Senior RTL Engineer, Memory Centric Computing
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOERequires a bachelor's degree with 5+ years, master's with 3+ years, or PhD with 0+ years of industry experience; strong microarchitecture, computer architecture, RTL, memory, interconnect, and AI/ML expertise.
Verilog, SystemVerilog, HLS, RTL, AI/ML
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
3mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
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Senior Staff RTL Verification Engineer
United States or Seattle
$159k-$238k/yr HybridFull Time
12+ YOEBachelor's in Electrical or Computer Engineering and 12+ years of RTL verification experience, or equivalent graduate-degree experience. Requires SystemVerilog, UVM, assertions, coverage, CI/CD, RTL tools, and scripting.
SystemVerilog, Universal Verification Methodology (UVM), Perl, Python, Ruby, UNIX shell, CI/CD
3mo
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RTL Feasibility Engineer, AI/ML Processors
Austin, Texas, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's in science/engineering required. Strong Python, Perl, Shell scripting; familiarity with SystemVerilog and RTL; experience with Git; experience in logic design, synthesis, timing and power analysis; strong communication and collaboration skills.
Python, Perl, Shell, SystemVerilog, RTL, Git, digital design simulator, design synthesis engine, power estimation engine
1w
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Senior RTL Design Engineer
Austin or San Jose
$120k-$200k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE, computer engineering, or computer science; 5+ years of ASIC RTL design experience; SystemVerilog, architecture, digital logic, synthesis, timing analysis, verification tools, Python, and Linux shell skills.
SystemVerilog, AXI, PCIe, Ethernet, HBM, DDR, Python, Linux shell, Git, FPGA
2mo
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FE RTL Infrastructure - CAD Engineer
Cupertino, California, United States
OnsiteFull Time
Design and build infrastructure for RTL/CAD to support next-generation high-performance, power-efficient processors and SoCs.
RTL, CAD, SoC
1mo
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HBM SoC RTL Design Engineer
Folsom, California, United States
$121k-$247k/yr OnsiteFull Time
3+ YOE3+ years SoC/RTL design experience, proficiency in SystemVerilog/Verilog, RTL-to-GDS flow knowledge, familiarity with EDA toolchains, scripting (Python/TCL/Perl/shell), and SoC integration skills.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell, Palladium, Veloce, Zebu
1mo
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RTL Design Engineer, TPU
Sunnyvale, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE/CS or equivalent, scripting experience, SystemVerilog and RTL design expertise, ASIC experience (8 years preferred), strong communication and cross-functional collaboration skills.
SystemVerilog, I2C, SPI, UART
1mo
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HBM SoC RTL Design Engineer
Folsom, California, United States
$121k-$247k/yr OnsiteFull Time
3+ YOEBachelor's or master's in EE/Computer Engineering with 3+ years experience, proficiency in SystemVerilog/Verilog, RTL‑to‑GDS flow, EDA tools, and scripting (Python/TCL/Perl/shell).
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, Tcl, Perl, Shell, Palladium, Veloce, Zebu
1mo
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Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
2mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
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