30 rtl engineer jobs at 15 companies in Arizona
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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
2w
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Senior Technical Staff Engineer - Verification
Bangalore or Chandler
OnsiteFull Time
15+ YOE15+ years functional verification experience; expertise in SystemVerilog, UVM, formal methods, RTL and SoC verification; BS/MS in EE/CE or related; strong communication, mentoring, and problem-solving skills.
SystemVerilog, UVM, Formal, RTL, AI/ML
2mo
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FPGA Engineer (Space)
Tempe, Arizona, United States
$133k-$210k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical/Computer Engineering; 6+ years FPGA design; SystemVerilog/VHDL; RTL design; lab/test experience; US citizenship; travel up to 10%
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Quartus, Synplify, MATLAB
3mo
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Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
4w
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Senior DfT Engineer
Chandler, Arizona, United States
HybridFull Time
3+ YOEMaster's (MSEE) in relevant fields, 3+ years DfT/digital design experience, strong RTL coding and verification skills, Verilog/SystemVerilog proficiency, problem solving and communication skills.
Verilog, SystemVerilog
3mo
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FPGA Engineer (AZ, Phoenix)
Phoenix, Arizona, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and hardware security systems; RTL, C/C++, Python, VHDL/Verilog; FPGA tools; security clearance.
VHDL, Verilog, SystemVerilog, Python, C, C++, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, AcE, AXI, Avalon
4w
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Senior Digital Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years digital design experience, degree in electrical/computer discipline, fluent Verilog/SystemVerilog, ASIC methodology, lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, willing to travel.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM with 5+ years (or equivalent advanced degree experience), RTL/HDL FPGA/ASIC design experience for space/aerospace, proficiency in FPGA design flow, simulation, synthesis, timing analysis, and V&V.
Xilinx ISE, Vivado, Mentor Graphics ModelSim, QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM)
2mo
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Digital IC Design & Firmware Engineer | Precision ADC
Tucson, Arizona, United States
OnsiteFull Time
2+ YOEMaster's in Electrical/Computer Engineering; 2+ years in digital design or embedded firmware; C for embedded; RTL with Verilog/SystemVerilog; digital logic fundamentals; problem-solving.
Verilog, SystemVerilog, C, Python, ModelSim, Xcelium, VCS
1w
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Test Engineer
San Jose or Austin or Pittsburgh or Tucson
$150k-$190k/yr OnsiteFull Time
5+ YOE5+ years fabless or IDM semiconductor test experience, hands-on DFT, ATPG/MBIST/JTAG, ATE bringup on Advantest or Teradyne, OSAT coordination, yield analysis, and strong communication skills.
DFT, ATPG, MBIST, JTAG, STIL, PDL, SVF, Advantest, Teradyne, Python, Perl, VCD, RTL
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FPGA Design Engineer
Tucson, Arizona, United States
OnsiteFull Time
8+ YOEB.S. in EE/CE, 8+ years FPGA design experience with VHDL, AMD/Xilinx/Vivado, RTL-to-hardware lifecycle, lab debugging, Git, ModelSim/QuestaSim, and scripting (Python/Perl/Ruby). U.S. work authorization required; clearance may be needed.
VHDL, AMD/Xilinx, Vivado, Git, ModelSim, QuestaSim, Python, Perl, Ruby, oscilloscope, spectrum analyzer, signal source, power supply
6d
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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
2mo
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Senior LPU ASIC Engineer
Santa Clara or California or North Carolina or Oregon or Arizona or Massachusetts or United States
$136k-$265k/yr HybridFull Time
5+ YOEB.S. in ECE or equivalent with 5+ years delivering full‑flow physical design for large SoCs; expertise in RTL-to-GDSII flow, low-power (UPF), timing/CTS, PPA optimization, sign-off integrity, DFT, and scripting (TCL/Python/Perl).
TCL, Python, Perl
1mo
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Senior ASIC Methodology Engineer - LPU Division
California or Texas or North Carolina or Arizona or Oregon or Massachusetts or United States
$152k-$288k/yr RemoteFull Time
5+ YOEBachelor's or Master's in CS/CE/EE (or equivalent), 5+ years industry experience, ASIC methodology and RTL/verification exposure, Python/Perl/Make/shell skills, experience with AI frameworks and strong communication.
Python, Perl, Make, Shell
3d
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Systems and Test Integration Engineer - FPGA Integration & Verification
Scottsdale, Arizona, United States
$91k-$101k/yr OnsiteFull Time
2+ YOEBachelor's in systems/engineering/math plus 2+ years (or Master's plus 6 months), TS/SCI clearance obtainable, FPGA design and hardware bring-up experience, RTL (SystemVerilog/VHDL), scripting (Python,Tcl), Linux and Git proficiency.
SystemVerilog, VHDL, Xilinx/AMD Vivado, Lattice Diamond, Radiant, Python, Tcl, Git, GitLab CI, RHEL, Ubuntu, Linux shell scripts, JTAG, oscilloscope, protocol analyzer
2w
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Confidential Computing Software Architect
Santa Clara or Alabama or Georgia or Florida or Colorado or California or Delaware or Arizona or Alaska or Belgium or France or Austria or Canada
OnsiteFull Time
Experienced in implementing system software for confidential compute, proficient in C, familiar with hypervisors, TEEs, peripheral security standards, and working with CPU/RTL teams.
RISC-V, C, Rust, Ada SPARK, Frama-C, PCI IDE, SPDM
1w
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Hardware Designer
Phoenix or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelors in Electrical/Computer Engineering, high-speed PCB and system design expertise, familiarity with FPGA and signal integrity, bench bring-up and test experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test set, signal analyzer, oscilloscope, VNA, signal generator
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Senior Engineering Manager API Platform
Minnesota or Arizona or New York or Illinois
$118k-$261k/yr RemoteFull Time
7+ YOE7+ Mgmt7+ years leadership managing ICs, 7+ years building enterprise applications, 5+ years JavaScript, 3+ years TypeScript and Node.js, experience with API gateways (Kong, Apigee, APIM), distributed workflows (Temporal), and strong security/authentication knowledge.
GraphQL, OAuth, OIDC, JWTs, Apigee, APIM, Kong, Temporal, JavaScript, TypeScript, Node.js, Git, Jest, RTL, Cypress, Playwright, Kubernetes, Docker, GHA, CI/CD
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