10 rtl engineer jobs at 2 companies in Caldwell, ID
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SR RTL DESIGN
Boise, Idaho, United States
OnsiteFull Time
4+ YOEMaster's in EE +4 yrs or Bachelor's in EE +5 yrs; proficiency in Verilog/SystemVerilog, RTL design and low-power methodologies (UPF, CDC/RDC), synthesis, STA, and RTL simulation; strong collaboration and PPA focus.
Verilog, SystemVerilog, UPF, CDC, RDC, RTL-to-GDS, lint, synthesis, logic synthesis, RTL simulation tools, static timing analysis
3d
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PRINICPAL RTL DESIGN
Boise, Idaho, United States
OnsiteFull Time
8+ YOEMaster's+8 years or Bachelor's+10 years pre-silicon RTL design experience; strong RTL, low-power (UPF), CDC/RDC, synthesis, STA, simulation, Verilog/SystemVerilog skills; DRAM experience preferred.
Verilog, SystemVerilog, lint, CDC, RDC, synthesis, Unified Power Format (UPF), static timing analysis (STA), simulation
2mo
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Principal RTL Design
Boise, Idaho, United States
OnsiteFull Time
8+ YOEMaster's EE with 8+ years or Bachelor's EE with 10+ years RTL/pre-silicon design; ownership of complex RTL/IP, low-power ASIC methodologies (UPF), Verilog/SystemVerilog, STA, synthesis, CDC/RDC experience.
Verilog, SystemVerilog, UPF, CDC, RDC, STA, lint, synthesis
3d
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PRINCIPAL RTL DESIGN
Boise, Idaho, United States
OnsiteFull Time
8+ YOEMaster's+8 years or Bachelor’s+10 years pre-silicon RTL design experience; proficiency in Verilog/SystemVerilog, UPF, CDC/RDC, STA, logic synthesis, and front-end simulation tools.
Verilog, SystemVerilog, UPF, CDC, RDC, STA
2mo
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Principal Circuit Design Engineer - DRAM Design
Boise, Idaho, United States
HybridFull Time
6+ YOEBachelor's in EE or equivalent, 6+ years digital/RTL circuit design, experience with RTL, STA, timing closure, power delivery network design, proficiency with UNIX and Cadence; master's and synthesis/IC compiler experience preferred.
RTL, STA, UNIX, Cadence, synthesis tools, IC compilers
3mo
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FPGA Engineer (Idaho, Boise)
Boise, Idaho, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
RTL, C/C++, Python, VHDL, Verilog, Tcl; hardware security; Xilinx; Vivado; IP core development; system integration; cryptography; hardware/software co-design; experience with simulation and verification tools; ability to obtain/maintain U.S. government security clearance.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, AXI, Avalon, ACE, IP core design, HDL
1w
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (Master's+3 acceptable), U.S. citizenship, ability to obtain DoD Secret clearance, 5–8+ years ASIC/FPGA RTL design experience, formal verification and verification-process experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office, STA
2w
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Senior Principal ASIC FPGA Engineer
Boise, Idaho, United States
$191k-$212k/yr HybridFull Time
10+ YOEBachelor's in EE/CE (or Master's) plus 10+ years (or 8+ with Master's), DoD Secret clearance, 10–15+ years ASIC/FPGA RTL design experience, full tape-out lifecycle, FinFET/node experience, EDA and verification expertise, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office
1w
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Lead ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$177k-$187k/yr RemoteFull Time
8+ YOEBachelor's in ECE or related plus 8+ years (or Master's plus 6+ years), strong RTL/ASIC/FPGA design experience, ASIC tape-out and timing closure experience, ability to obtain DoD Secret clearance, proficiency with JIRA and Microsoft Office.
JIRA, Microsoft Office
2w
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Staff Verification Design Engineer, DRAM
Boise, Idaho, United States
OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years verification experience,strong DRAM/memory architecture knowledge,proficiency with HSPICE and Python,and experience in circuit/system verification.
HSPICE, Python, Verilog, SPICE, STA, RTL