41 rtl engineer jobs at 12 companies in Camas, WA
2mo
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Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
1mo
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Sr. CPU RTL Front End Methodology Engineer
Austin or Phoenix or Hillsboro
$164k-$312k/yr OnsiteFull Time
6+ YOE5+ MgmtRequires 6+ years silicon CPU logic experience, 5+ years technical leadership; degree in CS/Electrical/Electronics engineering (or related) with substantial experience; experience with RTL methodologies, front-end and back-end flows, and use of AI tools.
AI tools
1mo
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FE RTL Infrastructure - CAD Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Design and build infrastructure for high-performance, power-efficient processors and system-on-chip technology; collaborate within silicon and manufacturing teams.
2mo
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Senior Engineer, Digital Design Engineering
Beaverton, Oregon, United States
$122k-$174k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2 years of digital design/verification experience; proficiency with RTL, Verilog/SystemVerilog, and CAD tools; knowledge of verification methods and test benches.
Verilog, SystemVerilog, Cadence, Synopsys, RTL design, Test benches, ASIC design flow
1w
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
5+ YOEExperience in SOC physical design, low-power methodology, RTL-to-GDS implementation, signoff (timing, physical verification, EMIR, formal equivalence), and collaboration across CAD, RTL, architecture, and power teams.
PrimePower
1mo
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Product Test Engineer
Hillsboro, Oregon, United States
OnsiteFull Time
6+ YOEMS with 6 years or BS with 8 years in Electrical/Electronics/Computer Engineering; experience with ATE, IC characterization, test methodologies, RTL/DFT, Verilog/VHDL, Python/C++; strong communication and problem-solving.
Nextest Magnum, Advantest T2K, Teradyne UltraFLEX, Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, WAT/etest, Verilog, VHDL, Python, C++, Windows, Unix, Microsoft Office
1w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with 8+ years ASIC/SoC design experience; RTL-to-silicon expertise, Synopsys/Cadence tool experience, Verilog/SV and scripting languages, strong communication and problem-solving skills.
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
6d
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
6d
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
1w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,experience with Synopsys and Cadence tools,proficiency in Verilog,SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
1w
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with VLSI focus,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,knowledge of Synopsys and Cadence flows,proficiency in Verilog/SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, Subversion, git, GitHub, FPGA, AI Copilot (LLM-based tools)
3w
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Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin or San Jose
$170k-$273k/yr OnsiteFull Time
8+ YOEB.S. or M.S. in electrical engineering,8+ years relevant experience,RTL/Verilog,Intel/Xilinx tool flows,static timing analysis,FPGA transceivers,EM simulation lab validation,C/C++,Linux/Windows proficiency.
C, C++, Verilog HDL, Intel/Xilinx FPGA tool flows, UVM, Linux, Windows, oscilloscope, power supply, waveform generator, ATE
1mo
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Senior Physical Design and Timing Engineer
Santa Clara or Austin or Hillsboro or Durham
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering with 5+ years or MS with 3+ years; strong static timing analysis, synthesis, physical design, timing convergence, RTL/logic understanding; proficiency with Perl, Tcl, Make, Python.
Perl, Tcl, Make, Python
1mo
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Senior Formal Verification Engineer
Santa Clara or Austin or Westford or Hillsboro
$168k-$311k/yr HybridFull Time
7+ YOE7+ years experience with formal verification, strong knowledge of Verilog/System Verilog, temporal logic assertions, abstraction techniques, scripting in TCL/Perl/Python, and solid understanding of CPU/GPU architectures.
Verilog, System Verilog, temporal logic assertions, TCL, Perl, Python, Jasper Gold, VC Formal, RTL
3w
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Senior CPU Performance Architect
Austin or Portland or Mountain View or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.
ARM, RISC-V, x86, RTL, Linux
1mo
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Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
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