20 rtl engineer jobs at 9 companies in Castle Pines, CO
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Senior Engineer, Digital Design Engineering
Colorado Springs, Colorado, United States
$112k-$167k/yr HybridFull Time
2+ YOEMaster's degree in Electrical or Electronic Engineering or Computer Science/Engineering; 2+ years in digital design/verification; RTL/Verilog/SystemVerilog expertise; Cadence or Synopsys tools.
Verilog, SystemVerilog, Cadence, Synopsys, RTL, Digital Design
1w
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Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
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Senior Electrical Engineer
Denver, Colorado, United States
$104k-$164k/yr HybridFull Time
8+ YOEBS Electrical Engineering with 8+ yrs (MS 6+ yrs) of hands-on, complex analog/digital/mixed-signal design; FPGA/RTL; PLM; EMC/patient-safety standards.
Altium Designer, MATLAB, Windchill, Verilog, SystemVerilog, PCB Layout, Oscilloscope, Multimeter, Logic Analyzer, Schematic Capture, FPGA Design, RTL Design
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ASIC Digital Design Engineer
Colorado Springs, Colorado, United States
$96k-$160k/yr OnsiteFull Time
0+ YOEBS in Electrical or Computer Engineering; 0–2 years designing and verifying digital or mixed-signal ASICs; ASIC/FPGA flows, DSP, RTL, object-oriented programming, and strong communication skills.
ASIC, DSP, RTL, FPGA
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
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Physical Design Engineer
Colorado Springs, Colorado, United States
$129k-$207k/yr OnsiteFull Time
12+ YOEBachelor's in Electrical/Electronics Engineering, 12+ years' RTL-to-tapeout physical design experience, TCL/PERL scripting, EDA tool proficiency, B2B communication and timing closure expertise.
TCL, PERL, EDA Tools
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Senior Electronics Engineer II
Westminster, Colorado, United States
$120k-$161k/yr OnsiteFull Time
6+ YOEBS in Electrical Engineering; 6+ years in board-level electronics design, analysis, and test; strong RTL/FPGA, HDL, SDR, and telemetry experience; excellent communication.
Altium Designer, Siwave, ADS SIPro, Mentor Hyperlynx
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
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FPGA Engineer (CO, Colorado Springs)
Colorado Springs, Colorado, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based hardware security systems; work with RTL/C/C++, Python, VHDL/Verilog; system integration and verification; travel up to 10%; requires ability to obtain/maintain U.S. Government security clearance.
C, C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Stratix, Agilex, Zynq, AXI, ACE, Avalon, cocotb, pyuvm
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Senior ASIC Digital / DSP Design Engineer
Colorado Springs, Colorado, United States
$142k-$236k/yr OnsiteFull Time
10+ YOEBS/MS in EE/CE,10+ years experience in digital/DSP/ASIC design and verification,RTL and DSP algorithm development,experience with ASIC/FPGA flows and verification,strong math and communication skills,US-person required.
Cadence, Mentor
2mo
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Software Development Engineer, Bespoke Solutions; ADC Hardware & Software Team
Denver, Colorado, United States
$144k-$194k/yr OnsiteFull Time
3+ YOEBachelor's degree (CS or equivalent), 3+ years system design/architecture, 2+ years system programming (C/C++/Rust), active TS/SCI clearance, embedded/firmware and security/crypto experience preferred.
Rust, C, C++, ARM, RISC-V, Linux, RTL, CI/CD, FPGA, AWS
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Solutions Architect
San Jose or Longmont
$203k-$348k/yr HybridFull Time
Experienced in FPGA/RTL, embedded systems, PCIe, DDR, Ethernet; strong C/C++, SystemVerilog.
SystemVerilog, Verilog, PCIe, CXL, DDR, Ethernet, AXI, Python, Tcl, Makefiles, Shell scripting, Linux kernel, IPC, RTOS, UVM, Palladium, Protium, Zebu
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