2mo
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Senior Electrical Engineer
Denver, Colorado, United States
$104k-$164k/yr HybridFull Time
8+ YOEBS Electrical Engineering with 8+ yrs (MS 6+ yrs) of hands-on, complex analog/digital/mixed-signal design; FPGA/RTL; PLM; EMC/patient-safety standards.
Altium Designer, MATLAB, Windchill, Verilog, SystemVerilog, PCB Layout, Oscilloscope, Multimeter, Logic Analyzer, Schematic Capture, FPGA Design, RTL Design
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
2mo
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Programmable Logic Design Engineer
Germantown or Carlsbad or Independence or Englewood
$156k-$246k/yr OnsiteContract
5+ YOEBachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.
System Verilog, Verilog, VHDL, Xilinx Vivado, RTL design, FPGA design, Testbench development, Simulation
1mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
3w
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Principal ASIC Design Engineer
Boulder or Austin
$180k-$220k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
10+ YOEMS/PhD in EE, 10+ years post-degree hardware experience, 2+ full ASIC design cycles, FPGA-to-ASIC experience, SystemVerilog/RTL proficiency, DSP RTL experience, knowledge of Cadence/Synopsys/Siemens EDA, mixed-signal background, mentoring experience.
RTL, SystemVerilog, Cadence, Synopsys, Siemens EDA, FPGA
2mo
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FPGA Engineer
Greenwood Village, Colorado, United States
$90k-$140k/yr OnsiteFull Time
B.S. or M.S. in Electrical and/or Computer Engineering; HDL RTL coding; FPGA experience; SystemVerilog; lab verification and documentation.
Xilinx Design Suite, Vivado, Chipscope, Quartus, ModelSim, QuestaSim, UVM, AMBA AXI, APB
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
2mo
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Senior Electronics Engineer II
Westminster, Colorado, United States
$120k-$161k/yr OnsiteFull Time
6+ YOEBS in Electrical Engineering; 6+ years in board-level electronics design, analysis, and test; strong RTL/FPGA, HDL, SDR, and telemetry experience; excellent communication.
Altium Designer, Siwave, ADS SIPro, Mentor Hyperlynx
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Experience with Perl/Python/C/shell scripting, Verilog/System Verilog/VHDL, RTL design and verification, and physical design (layout, timing, power). Master's in ECE or related accepted.
Perl, Python, C, Unix shell, Verilog, System Verilog, VHDL
1w
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SLD Avionics FPGA Engineer III - Lunar Permanence
Seattle or Denver
$120k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBachelor's/Master's in engineering or related field,5+ years FPGA/ASIC design and verification,RTL in Verilog/SystemVerilog/VHDL,FPGA tools and simulators,UVM/OVM testbenches,ability to travel ~10%,U.S. work authorization required.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Lattice Diamond, Radiant, Microchip Libero, ModelSim, QuestaSim, Perl, Python, Tcl, Git, SVN, AMBA, AXI, AHB, APB, IEEE 802.3, XAUI, JESD204, I2C, SPI, UVM, OVM
2w
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FPGA Engineer - Level 2 - New Glenn
Kent or Denver
$98k-$150k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
2+ YOEB.S. in EE/CE or related, 2+ years FPGA/ASIC design and verification, RTL in Verilog/SystemVerilog/VHDL, timing/CDC experience, FPGA tools experience, EMR not required, ability to communicate technical information.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Microchip Libero, QuestaSim, Linux, DOORS Next Generation, Git, SVN, AMBA, Universal Verification Methodology (UVM)
1mo
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Software Development Engineer, Bespoke Solutions; ADC Hardware & Software Team
Denver, Colorado, United States
$144k-$194k/yr OnsiteFull Time
3+ YOEBachelor's degree (CS or equivalent), 3+ years system design/architecture, 2+ years system programming (C/C++/Rust), active TS/SCI clearance, embedded/firmware and security/crypto experience preferred.
Rust, C, C++, ARM, RISC-V, Linux, RTL, CI/CD, FPGA, AWS
2mo
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Solutions Architect
San Jose or Longmont
$203k-$348k/yr HybridFull Time
Experienced in FPGA/RTL, embedded systems, PCIe, DDR, Ethernet; strong C/C++, SystemVerilog.
SystemVerilog, Verilog, PCIe, CXL, DDR, Ethernet, AXI, Python, Tcl, Makefiles, Shell scripting, Linux kernel, IPC, RTOS, UVM, Palladium, Protium, Zebu