9 rtl engineer jobs at 3 companies in Cheyenne, WY
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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
2w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
3w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
2w
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Digital Design RTL Engineer
Fort Collins or San Jose
OnsiteFull Time
Expert SystemVerilog RTL for advanced nodes, 8+ years experience, BSEE required (MSEE/PhD preferred), SoC integration experience, SerDes/DDR/HBM protocols, CDC/RDC, low-power and PPA optimization, timing closure and cross-team collaboration.
SystemVerilog
2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
3d
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
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CPU Cores Validation Senior Staff Engineer
Fort Collins, Colorado, United States
$178k-$268k/yr HybridFull Time
Experienced silicon validation engineer with strong programming (x86 assembly, C/C++, Perl, Ruby, Python), HDL knowledge (Verilog/System Verilog), DFT/JTAG familiarity, lab validation experience, and BS/MS in EE/CS/CSE.
x86 assembly, C, C++, Perl, Ruby, Python, Verilog HDL, System Verilog, JTAG -1149.x, BIST, LSSD/MuxD, RTL, DFT
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FPGA DSP Engineer
Fort Collins, Colorado, United States
$143k-$191k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE or related; 12+ years FPGA design experience; expert in RTL (SystemVerilog/VHDL), Xilinx toolchains (Vivado/Quartus), DSP implementation on FPGAs; FPGA verification and timing closure experience; eligible for U.S. Secret clearance.
SystemVerilog, VHDL, Vivado, Quartus, MATLAB, Git, Xilinx
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Senior Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
$156k-$268k/yr OnsiteFull Time
Experienced VLSI physical design engineer with hands-on high-speed design, chip floorplanning, CTS, P&R, STA, parasitic extraction, IR drop/EM analysis, Verilog RTL comprehension, scripting (Perl, C, tcl), and use of AI agents; BS/MS in EE/CS/CSE preferred.
Verilog, Perl, C, tcl, AI Agents