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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
1mo
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Senior FPGA Engineer
Chicago or New York City or London or United States or Canada or Europe or Asia
OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering, 3+ years FPGA/hardware experience, Verilog/System Verilog and RTL skills, FPGA design flow (synthesis, place & route, static timing), SoC and TCP/IP knowledge, lab debugging, EM/board characterization.
Verilog, System Verilog, RTL, TCP/IP, XILINX, ALTERA
2mo
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Senior FPGA Engineer
Chicago, Illinois, United States
$145k/yr OnsiteFull Time
10+ YOESenior FPGA/ASIC design with Verilog/SystemVerilog; RTL; timing; verification; Python/Bash; strong collaboration; BS in CS/EE; MS a plus.
Verilog, SystemVerilog, VHDL, Python, Bash, RTL
3w
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Hardware Engineer
Chicago, Illinois, United States
$200k-$225k/yr OnsiteFull Time
BS in EE/CE/CS or related, strong RTL design using SystemVerilog, C++ experience, verification and multi-clock-domain knowledge, Ethernet fundamentals, Python/Bash scripting, and strong debugging and collaboration skills.
SystemVerilog, C++, Python, Bash, FPGA, PMA (Physical Media Attachment), Ethernet, RTL
2mo
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FPGA Engineer (IL, Schaumburg)
Schaumburg, Illinois, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, C/C++, Python, VHDL/Verilog; hardware security; FPGA design and verification; system integration; cryptography concepts.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, Versal, Agilex, AXI, Avalon, cocotb, pyuvm
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
2mo
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FPGA Engineer (IL, Chicago)
Chicago, Illinois, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
3+ YOEProficient in RTL, C/C++, Python, VHDL, Verilog; experience with FPGA toolchains and hardware security; able to travel up to 10%; eligible for U.S. government security clearance.
Verilog, VHDL, SystemVerilog, C, C++, Python, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, Agilex, Stratix, AXI, ACE, Avalon, IP core, Coc otb, pyuvm
1w
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FPGA Engineer
Hoffman Estates, Illinois, United States
$150k-$200k/yr HybridFull Time
5+ YOEBachelor's in EE/CE/CS,5+ years FPGA system development for radar/RF/communications,strong RTL skills (SystemVerilog/Verilog/VHDL/HLS),experience with AMD/Xilinx or Intel platforms,EMBEDDED Linux familiarity,US work authorization and possible clearance.
AMD/Xilinx, Intel, SystemVerilog, Verilog, VHDL, HLS, Embedded Linux, SPI, AXI, DMA, FIFO
1w
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Campus FPGA Engineer (Intern)
Chicago, Illinois, United States
$250k/yr OnsiteInternship
Undergraduate or graduate concentration in EE/CS, FPGA and RTL experience (SystemVerilog/Verilog/VHDL), familiarity with C/C++/Python, prior hardware or low-level software internship experience, reliable availability.
SystemVerilog, Verilog, VHDL, C, C++, Python, lowRISC, RISC-V, CocoTB, Chisel, Opencore, Bluespec, HLS, OpenCL, Linux kernel, Raspberry Pi, Arduino
6d
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FPGA Developer
Chicago, Illinois, United States
$225k/yr OnsiteFull Time
Degree in EE/CE/CS/Physics/Math expected by Dec 2026–Jun 2027; proficiency in System Verilog/Verilog/VHDL and C/C++/Python; RTL data processing and strong algorithms and programming fundamentals.
System Verilog, Verilog, VHDL, C, C++, Python
2w
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Junior FPGA Developer
Chicago, Illinois, United States
$100k-$175k/yr OnsiteFull Time
BS/MS in EE/CE or related field, hands-on RTL design in Verilog/SystemVerilog, familiarity with ModelSim/QuestaSim/Vivado/Quartus and synthesis flow, Linux proficiency, Python/C/C++ a plus, eagerness to apply AI tools and learn HFT.
Verilog, SystemVerilog, ModelSim, QuestaSim, Vivado, Quartus, Linux, Python, C, C++
1mo
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Full Stack Engineer (Delivery Toolkit)
Atlanta or Austin or Chicago or Dallas or Houston
$93k-$112k/yr HybridFull Time
2+ YOEBachelor's degree or equivalent; 2+ years building web or backend services; strong TypeScript, Node.js, FastAPI/Python, SQL/Postgres, testing, and practical AWS experience; familiarity with CI/CD, Docker, and IaC.
Svelte, SvelteKit, React, TypeScript, Node.js, Python, FastAPI, Zod, Pydantic v2, PostgreSQL, SQL, SQLAlchemy, Docker, Vitest, RTL, Jest, pytest, Playwright, OpenAPI, GitHub Actions, Cursor, GitHub Copilot, S3, RDS, Lambda, ECS, CloudWatch, IAM, API Gateway, SQS, SNS, EventBridge, ECR, Terraform, CloudFormation, CDK