Brookhaven National Laboratory: Conducts multidisciplinary scientific research and operates national user facilities.
7+ YOEBachelor's in EE/CE/applied physics, 7+ years digital ASIC design, SystemVerilog/Verilog RTL, CAD/EDA tool experience, strong timing/CDC/low-power knowledge, and collaboration with mixed-signal, verification, and firmware teams.
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.