2mo
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Senior Engineer, Digital Design Engineering
Wilmington, Massachusetts, United States
$124k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital/mixed-signal design and verification; proficiency with RTL, Verilog/SystemVerilog; experience with Cadence or Synopsys tools.
Verilog, SystemVerilog, RTL, Cadence, Synopsys
3d
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Sr. ASIC Design Engineer, Blink/Ring ASIC Team
North Reading, Massachusetts, United States
$159k-$215k/yr OnsiteFull Time
Bachelor's in Electrical Engineering, knowledge of UVM and Matlab, experience delivering products to volume production, low-power design expertise, RTL coding and debug, and leadership in technical initiatives.
UVM, Matlab, RTL
3w
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General Support Engineer – Aerospace, Defense & Government (ADG)
Portsmouth, New Hampshire, United States
$96k-$139k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CE,3+ years hardware support or board-level engineering,FPGA and RTL (Verilog/SystemVerilog) experience,lab debug with oscilloscopes/logic/protocol analyzers,Tcl/Python/Java scripting,eligible for U.S. security clearance.
Verilog, SystemVerilog, RTL, DDR, PCIe, Ethernet, Oscilloscope, Logic Analyzer, Protocol Analyzer, Tcl, Python, Java, FPGA
1mo
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Customer Projects Hardware Engineer – Aerospace, Defense & Government (ADG)
Hazlet or Portsmouth
$135k-$195k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CE or related, 6+ years hardware design/RTL/board-level experience, FPGA systems familiarity, high-speed interface knowledge (DDR, PCIe, Ethernet), lab debugging experience, eligible for U.S. security clearance.
oscilloscope, logic analyzer, RTL, PCIe, Ethernet, DDR
4d
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Senior Verification Engineer
Wilmington, Massachusetts, United States
$110k-$152k/yr OnsiteFull Time
4+ YOE4+ years verification experience with SystemVerilog/UVM, RTL simulation and debug, scripting (Python/Perl/Tcl), SoC/processor verification, and strong analytical/debugging skills.
SystemVerilog, UVM, VCS, Xcelium, Simvision, Verdi, Questa, Python, Perl, Tcl, Linux, ARM Cortex-M, RISC-V, APB, AHB, AXI, QSPI, UART, DMA
2d
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Staff FPGA Systems Development Engineer
Durham or Wilmington
$125k-$181k/yr OnsiteFull Time
Bachelor's in electrical/computer engineering, strong FPGA/SoC and RTL experience, familiarity with Intel/Altera or AMD-Xilinx, proficiency in C/C++, Python, TCL, strong communication and coordination skills.
Intel-Altera, AMD-Xilinx, C, C++, Python, TCL, Electronic Test Equipment
3w
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
1mo
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
4d
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Staff Engineer, Digital Design Engineering
Chelmsford, Massachusetts, United States
$135k-$202k/yr OnsiteFull Time
8+ YOEExpertise in FPGA/ASIC RTL and schematic capture, board-level design, high-speed interfaces, Verilog/VHDL, simulation, and collaboration; U.S. citizenship and ability to obtain Secret clearance required; preferred 8+ years digital design experience.
Verilog, VHDL, 100 GigE, Aurora, PCIe, Allegro, PADS, C#, Python, C/C++, TCL
1mo
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Principal Digital Design Engineer (ASIC)
Somerset or Wilmington
$160k-$239k/yr OnsiteFull Time
10+ YOE10+ years ASIC/SoC digital design experience, Bachelor’s degree in EE/CE, expertise in SystemVerilog/Verilog, RTL design, synthesis, timing closure, MATLAB/TCL/Python modeling, Cadence tools, and tapeout experience.
SystemVerilog, MATLAB, Verilog, Python, TCL, Cadence, UVM
2mo
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Senior FPGA Design Engineer
Manchester or Nashua
$97k-$165k/yr OnsiteFull Time
4+ YOEU.S. person required and able to obtain Secret clearance; typically Bachelor's degree with 4+ years relevant experience; FPGA/ASIC design, RTL coding (VHDL/Verilog), synthesis, timing closure, lab debug, and familiarity with high-speed interfaces and revision control.
FPGA, VHDL, Verilog HDL, Xilinx Vivado, Intel/Altera Quartus, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, SERDES, PCIe, DDR2/3/4, LVDS
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr HybridFull Time
Experience in ASIC design and digital/mixed-signal verification, test plan and testbench development, SystemVerilog/UVM, RTL and functional coverage, formal verification, and scripting (Unix/Linux shell, Perl, Python).
SystemVerilog, UVM, Unix/Linux shell, Perl, Python
1mo
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SatCom, ISR & Space Payload Architect
Portsmouth or San Jose
$169k-$245k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE (Master's preferred), 8+ years in SatCom/ISR/space payload design, FPGA (VHDL/Verilog/SystemVerilog) and DSP experience, familiarity with PCIe/Ethernet/JESD204, eligible for U.S. security clearance.
VHDL, Verilog, SystemVerilog, RTL, PCIe, Ethernet, JESD204, Altera FPGA architecture and toolchain