17 rtl engineer jobs at 7 companies in Elon, NC
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Fall 2026 Co-Op - Digital Design Engineer
Greensboro, North Carolina, United States
HybridInternship
Pursuing MS or PhD in Electrical Engineering or related field; strong DSP knowledge; proficiency in Verilog, Synopsys flows, and Matlab; experience with RTL design, simulation, and verification.
Verilog, Synopsys, Matlab
1mo
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
5d
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Staff FPGA Systems Development Engineer
Durham or Wilmington
$125k-$181k/yr OnsiteFull Time
Bachelor's in electrical/computer engineering, strong FPGA/SoC and RTL experience, familiarity with Intel/Altera or AMD-Xilinx, proficiency in C/C++, Python, TCL, strong communication and coordination skills.
Intel-Altera, AMD-Xilinx, C, C++, Python, TCL, Electronic Test Equipment
1mo
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Senior Staff Engineer, Digital IC Design
Morrisville, North Carolina, United States
$136k-$201k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE (5+ years) or MS/PhD (3+ years); strong SystemVerilog RTL, SoC and multi-clock design, RTL/synthesis/timing/verification expertise, SVA/formal knowledge; Python/Perl/Tcl/UNIX shell desirable; strong communication and documentation.
SystemVerilog, SVA, AXI, DDR, Ethernet, PCIe, Python, Perl, Tcl, UNIX shell
1mo
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Senior Physical Design and Timing Engineer
Santa Clara or Austin or Hillsboro or Durham
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering with 5+ years or MS with 3+ years; strong static timing analysis, synthesis, physical design, timing convergence, RTL/logic understanding; proficiency with Perl, Tcl, Make, Python.
Perl, Tcl, Make, Python
1mo
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FPGA Systems Development Engineer
Copenhagen or Durham
OnsiteFull Time
Bachelor's in electrical/computer engineering, hands-on FPGA/SoC programming experience, strong communication and problem-solving, ability to work on multiple projects and deliver high-quality results.
FPGA, SoC, HDL, IP, RTL, Intel-Altera, AMD-Xilinx, C/C++, Python, TCL, ATE
2mo
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Senior ASIC Power Engineer
Santa Clara or Austin or Durham or United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBS or MS in electrical engineering or computer science; 5+ years in high-performance processor designs; SystemVerilog or HDL; VLSI/physical design; strong communication; computer architecture.
SystemVerilog, HDL, VLSI, RTL
2mo
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Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer
Durham, North Carolina, United States
$131k-$190k/yr OnsiteFull Time
10+ YOE10+ years of experience, including 5 years in digital IC design; expertise in digital signal processing, RTL design, digital architecture; firmware and embedded software; radio architecture; microprocessor subsystems; experience across hardware-software co-design.
SystemVerilog, MATLAB, Python, DSP cores
1mo
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Senior ASIC Design Engineer - Agentic AI
Santa Clara or Durham or Austin
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent, 8+ years experience, expertise in micro-architecture and RTL (Verilog), ASIC design flow, Python proficiency, and experience with LLM fine-tuning, RAG pipelines and vector databases.
Verilog, Python, large language models, RAG pipelines, vector databases
1mo
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Senior ASIC Design Engineer - Agentic AI
Santa Clara or Austin or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent experience, 8+ years experience, micro-architecture and RTL (Verilog) expertise, ASIC design flow knowledge, Python prototyping, experience with LLM fine-tuning, RAG pipelines, and vector databases.
Verilog, Python, RAG pipelines, vector databases, large language models
2mo
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Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)
1mo
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Senior Physical Design and Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in EE/CE with 5+ years or MS with 3+ years experience; expertise in STA, synthesis, physical design and timing convergence; experience with EDA tools; proficiency in Perl, Tcl, Make, Python; strong RTL and timing closure skills.
Electronic Design Automation (EDA), Static Timing Analysis (STA), Perl, Tcl, Make, Python
1mo
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ASIC Physical Design Technical Lead
San Jose or Austin or Research Triangle Park
$184k-$264k/yr OnsiteFull Time
3+ YOEBachelor/Master/PhD in Electrical Engineering with 3+–8+ years physical design experience; RTL-to-GDSII tapeout experience at advanced nodes; experience with Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, and Python.
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, Python, UPF
1mo
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MTS Digital Engineering
Morrisville, North Carolina, United States
$58k-$108k/yr HybridFull Time
0+ YOEBS EE (2-3 years) or MS EE/CE (0-1 year). Strong digital RTL design experience with Verilog/SystemVerilog, STA/CDC/Lint/DFT/BIST tools, plus Python/Perl scripting and simulation/debug skills.
SystemVerilog, Verilog, Python, Perl, Static Timing Analysis (STA), LEC, CDC, RDC, Lint, DFT, BIST
2mo
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Senior GPU Memory Architect
Santa Clara or Durham or Austin
$184k-$357k/yr OnsiteFull Time
6+ YOEMaster's (or equivalent) in EE/CS/CE, 6+ years in GPU/CPU architecture focused on memory caching and interconnects, B.S./PhD optional, strong communication and mentoring experience, familiarity with performance simulation, RTL, and silicon debug.
RTL
1mo
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Senior ASIC Physical Design Engineering Technical Lead
San Jose or Austin or Research Triangle Park
$211k-$305k/yr HybridFull Time
5+ YOEAdvanced degree in Electrical Engineering with significant physical design experience (BSc+12y / MSc+8y / PhD+5y), RTL-to-GDSII/tapeout experience at 7nm/5nm/3nm, EDA tool proficiency, UPF low-power methods, Python and AI tools experience.
Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, Python, RTL2GDSII, Flex-HTree, AI tools
3mo
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Senior System Simulation Architect
Santa Clara or Durham or Austin or Hillsboro
$184k-$357k/yr OnsiteFull Time
6+ YOEBS/MS in EE/CE/CS or equivalent; 6+ years relevant experience; strong C, C++, Python skills; experience with functional simulators or low-level software (OS/firmware/drivers); ARM ISA experience and strong debugging skills.
C, C++, Python, ARM ISA, Linux, CUDA, PyTorch, TensorFlow, SimPoint, FPGAs, RTL simulators, hardware emulators
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