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4 rtl engineer jobs at 2 companies in Elsmere, DE

2mo
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FPGA Engineer
Exton, Pennsylvania, United States
OnsiteFull Time
Innovative Solutions & Support
Innovative Solutions & SupportNASDAQ: ISSC: Manufacturer of aircraft cockpit displays and flight navigation systems.
2+ YOEBachelor's in Electrical Engineering; 2+ years FPGA/ASIC in regulated environments; proficient in Verilog/VHDL; Xilinx Vivado; DO-254 familiarity; hardware debugging; cross-functional collaboration
Verilog, VHDL, Xilinx Vivado, RTL simulation, ModelSim/Questa, DO-254 knowledge, I2C, SPI, JTAG, Ethernet, PCIe
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3mo
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FPGA Engineer (NJ, Moorestown)
Moorestown, New Jersey, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Familiar with RTL, C/C++, Python, VHDL/Verilog, hardware security, FPGA design, and hardware-software integration; eligible for U.S. government security clearance; willingness to travel ~10%.
VHDL, Verilog, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm, Python, C, C++, Tcl
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11h
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
Fairwinds Technologies
Fairwinds Technologies: Designing and integrating communication systems for defense agencies
10+ YOEBachelor's in EE/CE,10+ years FPGA design experience with Xilinx Vivado, Verilog/VHDL, RFSoC/Versal platforms, RTL-to-hardware validation, AXI interfaces, and eligibility for DoD Secret clearance.
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Versal, Versal ACAP, ADRV9009, AD9081, ADRV9009-ZU11EG, AXI-Lite, AXI-Stream, JESD204B, JESD204C, JTAG, Integrated Logic Analyzer (ILA), VIO, Ethernet, PCIe, Tcl, Python
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1mo
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
Fairwinds Technologies
Fairwinds Technologies: Designing and integrating communication systems for defense agencies
10+ YOEBachelor's in EE/CE, 10+ years FPGA design experience, strong Verilog/VHDL and Xilinx Vivado skills, RFSoC/Versal experience, RTL simulation and hardware debug experience, U.S. citizenship and Secret clearance (or ability to obtain).
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Integrated Logic Analyzer (ILA), VIO, JTAG, ADRV9009, AD9081, JESD204B/C, Ethernet, PCIe, Aurora, AXI-Lite, AXI-Stream, DMA, Tcl, Python
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