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Sr. RTL Engineer
Orlando, Florida, United States
OnsiteFull Time
5+ YOESenior FPGA/RTL engineer with SystemVerilog, FPGA design, modeling, simulation, verification, and test; knowledge of DSP, firmware, and hardware integration.
SystemVerilog, Verilog, Python, FPGA design, HDL Synthesis, VCS, Synplify, Git, Jira
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RTL Design Engineer
Melbourne, Florida, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; strong RTL design with Verilog/SystemVerilog; front-end tools; mixed-signal concepts; scripting; GenAI tools; strong communication.
Verilog, SystemVerilog, Verilog simulators, linters, CDC, RDC, LEQ, UPF, scripting languages
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Staff RTL Engineer
Orlando, Florida, United States
OnsiteFull Time
7+ YOEStaff RTL Engineer with FPGA/RTL design, SystemVerilog, modelling, simulation, verification, integration and test; derive FPGA requirements from system; perform RTL design and testing.
SystemVerilog, Verilog, Python, FPGA design tools, HDL synthesis, VCS, Synplicity
2mo
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SLD FPGA Verification Engineer III - Lunar Permanence
Seattle or Space Coast
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBS/MS in Electrical or Computer Engineering; 5+ years FPGA/ASIC verification; RTL simulation tools; UVM; testbench development; DO-254 knowledge a plus.
QuestaSim, ModelSim, SystemVerilog, UVM, RTL, DO-254
2mo
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FPGA Engineer (FL, Tampa)
Tampa, Florida, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, C/C++, Python; VHDL/Verilog; FPGA design and verification; cryptography and hardware security; system integration; agile environments.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, IP core, pyuvm, cocotb