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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
2mo
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Senior Electrical Engineer
Denver, Colorado, United States
$104k-$164k/yr HybridFull Time
8+ YOEBS Electrical Engineering with 8+ yrs (MS 6+ yrs) of hands-on, complex analog/digital/mixed-signal design; FPGA/RTL; PLM; EMC/patient-safety standards.
Altium Designer, MATLAB, Windchill, Verilog, SystemVerilog, PCB Layout, Oscilloscope, Multimeter, Logic Analyzer, Schematic Capture, FPGA Design, RTL Design
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
2mo
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Programmable Logic Design Engineer
Germantown or Carlsbad or Independence or Englewood
$156k-$246k/yr OnsiteContract
5+ YOEBachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.
System Verilog, Verilog, VHDL, Xilinx Vivado, RTL design, FPGA design, Testbench development, Simulation
1mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
2mo
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FPGA Engineer
Greenwood Village, Colorado, United States
$90k-$140k/yr OnsiteFull Time
B.S. or M.S. in Electrical and/or Computer Engineering; HDL RTL coding; FPGA experience; SystemVerilog; lab verification and documentation.
Xilinx Design Suite, Vivado, Chipscope, Quartus, ModelSim, QuestaSim, UVM, AMBA AXI, APB
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
2mo
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Senior Electronics Engineer II
Westminster, Colorado, United States
$120k-$161k/yr OnsiteFull Time
6+ YOEBS in Electrical Engineering; 6+ years in board-level electronics design, analysis, and test; strong RTL/FPGA, HDL, SDR, and telemetry experience; excellent communication.
Altium Designer, Siwave, ADS SIPro, Mentor Hyperlynx
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Experience with Perl/Python/C/shell scripting, Verilog/System Verilog/VHDL, RTL design and verification, and physical design (layout, timing, power). Master's in ECE or related accepted.
Perl, Python, C, Unix shell, Verilog, System Verilog, VHDL
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FPGA DSP Engineer
Fort Collins, Colorado, United States
$143k-$191k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE or related; 12+ years FPGA design experience; expert in RTL (SystemVerilog/VHDL), Xilinx toolchains (Vivado/Quartus), DSP implementation on FPGAs; FPGA verification and timing closure experience; eligible for U.S. Secret clearance.
SystemVerilog, VHDL, Vivado, Quartus, MATLAB, Git, Xilinx
1mo
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Software Development Engineer, Bespoke Solutions; ADC Hardware & Software Team
Denver, Colorado, United States
$144k-$194k/yr OnsiteFull Time
3+ YOEBachelor's degree (CS or equivalent), 3+ years system design/architecture, 2+ years system programming (C/C++/Rust), active TS/SCI clearance, embedded/firmware and security/crypto experience preferred.
Rust, C, C++, ARM, RISC-V, Linux, RTL, CI/CD, FPGA, AWS
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