Fuquay-Varina • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Fuquay-Varina • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Fuquay-Varina • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Fuquay-Varina • 50 milesRemote · Hybrid · Onsite · Field · All Environments
18 rtl engineer jobs at 8 companies in Fuquay-Varina, NC
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
2mo
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Senior Staff Engineer, Digital IC Design
Morrisville, North Carolina, United States
$136k-$201k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE (5+ years) or MS/PhD (3+ years); strong SystemVerilog RTL, SoC and multi-clock design, RTL/synthesis/timing/verification expertise, SVA/formal knowledge; Python/Perl/Tcl/UNIX shell desirable; strong communication and documentation.
SystemVerilog, SVA, AXI, DDR, Ethernet, PCIe, Python, Perl, Tcl, UNIX shell
4w
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Senior Silicon Engineer
Redmond or Mountain View or Santa Clara or Austin or Raleigh or Hillsboro or Boise
$120k-$235k/yr HybridFull Time
5+ YOEExperience verifying silicon using UVM/C, strong RTL and SoC verification background, proficiency with Verilog/System Verilog, and relevant EE/CS/CE degree or equivalent experience.
UVM, C, Verilog, System Verilog, Microsoft Excel
2w
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Staff FPGA Systems Development Engineer
Durham or Wilmington
$125k-$181k/yr OnsiteFull Time
Bachelor's in electrical/computer engineering, strong FPGA/SoC and RTL experience, familiarity with Intel/Altera or AMD-Xilinx, proficiency in C/C++, Python, TCL, strong communication and coordination skills.
Intel-Altera, AMD-Xilinx, C, C++, Python, TCL, Electronic Test Equipment
3d
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
1+ YOERequires a relevant engineering or computer science degree and 1–5+ years of technical engineering experience; preferred experience includes semiconductor physical design, tape-outs, low-power methods, and signoff workflows.
synthesis, place-and-route, clock construction, CTS, RTL, DFT, RTL to GDS, EMIR, formal equivalence, low-power verification
1mo
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Principal Firmware Engineer
Mountain View or Redmond or Hillsboro or Raleigh or Austin
$143k-$275k/yr HybridFull Time
SoC/firmware architecting, silicon bring-up, root-cause debug across RTL and firmware; doctoral/masters/bachelors in EE/CE/CS or equivalent experience; ability to pass Microsoft Cloud Background Check.
JTAG, ARMDS, Lauterbach TRACE32, ATE, Linux, Windows, Microsoft Excel
11h
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Senior Physical Design Engineer
Raleigh or Austin or Redmond or Hillsboro or Mountain View or New York or California
$120k-$235k/yr HybridFull Time
1+ YOEDegree in electrical, computer, or software engineering plus 1–5+ years of technical experience; preferred semiconductor physical design, tape-out, low-power, clock, signoff, and cross-functional collaboration experience.
synthesis, place-and-route, clock tree synthesis (CTS), RTL, DFT, GDS, CAD, SOC, EMIR
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Senior Physical Design and Timing Engineer
Santa Clara or Austin or Hillsboro or Durham
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical or Computer Engineering with 5+ years or MS with 3+ years; strong static timing analysis, synthesis, physical design, timing convergence, RTL/logic understanding; proficiency with Perl, Tcl, Make, Python.
Perl, Tcl, Make, Python
2mo
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Senior ASIC Power Engineer
Santa Clara or Austin or Durham or United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBS or MS in electrical engineering or computer science; 5+ years in high-performance processor designs; SystemVerilog or HDL; VLSI/physical design; strong communication; computer architecture.
SystemVerilog, HDL, VLSI, RTL
1mo
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FPGA Systems Development Engineer
Copenhagen or Durham
OnsiteFull Time
Bachelor's in electrical/computer engineering, hands-on FPGA/SoC programming experience, strong communication and problem-solving, ability to work on multiple projects and deliver high-quality results.
FPGA, SoC, HDL, IP, RTL, Intel-Altera, AMD-Xilinx, C/C++, Python, TCL, ATE
2w
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Senior Security IP Engineer
Mountain View or Hillsboro or Austin or Redmond or Raleigh
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS plus multiple years hardware design experience; expertise in RTL, CDC/RDC/LINT/STA, cryptographic hardware, and silicon bring-up; proficiency in Verilog/SystemVerilog and scripting.
Verilog, System Verilog, Python, Perl, AMBA AXI
2mo
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Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer
Durham, North Carolina, United States
$131k-$190k/yr OnsiteFull Time
10+ YOE10+ years of experience, including 5 years in digital IC design; expertise in digital signal processing, RTL design, digital architecture; firmware and embedded software; radio architecture; microprocessor subsystems; experience across hardware-software co-design.
SystemVerilog, MATLAB, Python, DSP cores
1mo
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Senior ASIC Design Engineer - Agentic AI
Santa Clara or Austin or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent experience, 8+ years experience, micro-architecture and RTL (Verilog) expertise, ASIC design flow knowledge, Python prototyping, experience with LLM fine-tuning, RAG pipelines, and vector databases.
Verilog, Python, RAG pipelines, vector databases, large language models
2mo
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ASIC Physical Design Technical Lead
San Jose or Austin or Research Triangle Park
$184k-$264k/yr OnsiteFull Time
3+ YOEBachelor/Master/PhD in Electrical Engineering with 3+–8+ years physical design experience; RTL-to-GDSII tapeout experience at advanced nodes; experience with Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, and Python.
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, Python, UPF
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MTS Digital Engineering
Morrisville, North Carolina, United States
$58k-$108k/yr HybridFull Time
0+ YOEBS EE (2-3 years) or MS EE/CE (0-1 year). Strong digital RTL design experience with Verilog/SystemVerilog, STA/CDC/Lint/DFT/BIST tools, plus Python/Perl scripting and simulation/debug skills.
SystemVerilog, Verilog, Python, Perl, Static Timing Analysis (STA), LEC, CDC, RDC, Lint, DFT, BIST
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Senior ASIC Physical Design Engineering Technical Lead
San Jose or Austin or Research Triangle Park
$211k-$305k/yr HybridFull Time
5+ YOEAdvanced degree in Electrical Engineering with significant physical design experience (BSc+12y / MSc+8y / PhD+5y), RTL-to-GDSII/tapeout experience at 7nm/5nm/3nm, EDA tool proficiency, UPF low-power methods, Python and AI tools experience.
Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, Python, RTL2GDSII, Flex-HTree, AI tools
2w
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Principal Subsystem Design Manager
Mountain View or Raleigh
$143k-$275k/yr HybridFull Time
8+ YOEAdvanced degree or equivalent experience in EE/CE/CS with 6–8+ years engineering experience, expertise in digital logic, RTL/Verilog/SystemVerilog, synthesis and PPA, post-silicon debug, and leadership; ability to pass security and export-control screenings.
Verilog, SystemVerilog, Python, Perl
2w
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Hardware Designer
Raleigh or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelor's in Electrical/Computer Engineering or equivalent, strong high-speed circuit and PCB design skills, FPGA familiarity, prototype bring-up and lab verification experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test sets, signal analyzers, GHz+ oscilloscopes, VNAs, signal generators
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