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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
5+ YOEExperience in SOC physical design, low-power methodology, RTL-to-GDS implementation, signoff (timing, physical verification, EMIR, formal equivalence), and collaboration across CAD, RTL, architecture, and power teams.
PrimePower
2w
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Fall 2026 Co-Op - Digital Design Engineer
Greensboro, North Carolina, United States
HybridInternship
Pursuing MS or PhD in Electrical Engineering or related field; strong DSP knowledge; proficiency in Verilog, Synopsys flows, and Matlab; experience with RTL design, simulation, and verification.
Verilog, Synopsys, Matlab
1mo
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
1mo
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Senior Staff Engineer, Digital IC Design
Morrisville, North Carolina, United States
$136k-$201k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE (5+ years) or MS/PhD (3+ years); strong SystemVerilog RTL, SoC and multi-clock design, RTL/synthesis/timing/verification expertise, SVA/formal knowledge; Python/Perl/Tcl/UNIX shell desirable; strong communication and documentation.
SystemVerilog, SVA, AXI, DDR, Ethernet, PCIe, Python, Perl, Tcl, UNIX shell
1d
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Staff FPGA Systems Development Engineer
Durham or Wilmington
$125k-$181k/yr OnsiteFull Time
Bachelor's in electrical/computer engineering, strong FPGA/SoC and RTL experience, familiarity with Intel/Altera or AMD-Xilinx, proficiency in C/C++, Python, TCL, strong communication and coordination skills.
Intel-Altera, AMD-Xilinx, C, C++, Python, TCL, Electronic Test Equipment
5d
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Senior ASIC Design Engineer
Santa Clara or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMasters in EE/CE (or equivalent),8+ years ASIC design experience,micro-architecture and RTL in Verilog,ASIC flow knowledge,EMR not applicable.
Verilog, Python, Perl, C, C++
1mo
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ASIC Physical Design Technical Lead
San Jose or Austin or Research Triangle Park
$184k-$264k/yr OnsiteFull Time
3+ YOEBachelor/Master/PhD in Electrical Engineering with 3+–8+ years physical design experience; RTL-to-GDSII tapeout experience at advanced nodes; experience with Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, and Python.
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, Python, UPF
1mo
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MTS Digital Engineering
Morrisville, North Carolina, United States
$58k-$108k/yr HybridFull Time
0+ YOEBS EE (2-3 years) or MS EE/CE (0-1 year). Strong digital RTL design experience with Verilog/SystemVerilog, STA/CDC/Lint/DFT/BIST tools, plus Python/Perl scripting and simulation/debug skills.
SystemVerilog, Verilog, Python, Perl, Static Timing Analysis (STA), LEC, CDC, RDC, Lint, DFT, BIST
2d
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Hardware Designer
Raleigh or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelor's in Electrical/Computer Engineering or equivalent, strong high-speed circuit and PCB design skills, FPGA familiarity, prototype bring-up and lab verification experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test sets, signal analyzers, GHz+ oscilloscopes, VNAs, signal generators
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