9 rtl engineer jobs at 4 companies in Granby, CO
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Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
3w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
2w
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
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Summer 2027 Intern - Hardware Engineering
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$34-$47/hr HybridInternship
0+ YOEEarly-career candidates pursuing or holding technical degrees in engineering or related fields; experience via coursework, internships, projects; familiarity with programming, embedded systems, digital logic, or hardware design; strong analytical and communication skills.
RTL, Verilog/SystemVerilog, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, CAD, Git, Linux, Microsoft Office, RTOS
2w
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Senior Product Planning Engineer - Simulation, Security, and Deployment
San Jose or Longmont
$144k-$246k/yr HybridFull Time
Deep expertise in UVM, SystemVerilog, RTL simulation, formal methods, and multi-language simulation; experience with EDA product roadmaps, AI agents, enterprise deployment, licensing, and executive communication.
AMD Vivado, UVM, SystemVerilog, HDL, VHDL, Verilog, Vivado Simulator, Xcelium, Questa, Riviera, AI agents, copilots
2d
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2027 PhD Research Engineering Intern/Co-op
Austin or Boxborough or Fort Collins or Longmont or Fishkill or Rochester or Secaucus
$92k-$137k/yr HybridInternship, Temporary
Current PhD student at a US university in computer science, computer engineering, electrical engineering, or related field; knowledge of listed programming, hardware, ML, or systems technologies encouraged.
C, C++, Verilog HDL, Python, P4, ML frameworks, Java, MATLAB, Go, FPGA, ASIC, RTL, GPUs, PyTorch, TensorFlow
3mo
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Solutions Architect
San Jose or Longmont
$203k-$348k/yr HybridFull Time
Experienced in FPGA/RTL, embedded systems, PCIe, DDR, Ethernet; strong C/C++, SystemVerilog.
SystemVerilog, Verilog, PCIe, CXL, DDR, Ethernet, AXI, Python, Tcl, Makefiles, Shell scripting, Linux kernel, IPC, RTOS, UVM, Palladium, Protium, Zebu