8 rtl engineer jobs at 4 companies in Keene, TX
1w
Save
Mark Applied
Hide
Digital IC Design Engineer
Dallas, Texas, United States
OnsiteFull Time
5+ YOERequires 5+ years of digital design experience, digital logic expertise, RTL-to-GDSII experience, and familiarity with Verilog and digital simulators. Scripting, interfaces, SystemVerilog, UVM, and ASIL experience preferred.
Verilog, SystemVerilog, UVM, Claude, I2C, SPI, SPMI, ARM, RTL, GDSII
2d
Save
Mark Applied
Hide
Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
1+ YOEBachelor's degree in electrical engineering or related field and 1+ year of AMS design verification experience. Preferred: SystemVerilog, UVM, RTL simulation, verification methodologies, and Python, Tcl, or Perl scripting.
SystemVerilog, UVM, Cadence Xcelium, Python, Tcl, Perl
4d
Save
Mark Applied
Hide
Associate Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
0+ YOEBachelor's degree in a relevant engineering or computer science field and 0–2 years of digital design verification experience. Requires SystemVerilog, RTL, verification, scripting, protocol, debugging, and collaboration skills.
SystemVerilog, Verilog, Python, Perl, Tcl, I2C, SPI, UART, Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA)
2mo
Save
Mark Applied
Hide
Digital IC Design Engineer | Custom
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's in EE/ECE/Computer Engineering, 8 years engineering experience including 3 years mixed-signal design verification, experience with Gates+SDF timing verification, automation scripting, and mixed-signal verification flows.
JasperGold, Gates+SDF, RTL, STA
2mo
Save
Mark Applied
Hide
Digital IC Design Engineer
Dallas, Texas, United States
OnsiteFull Time
1+ YOEBachelor's in EE/CE or related; 1+ years digital IC design experience; proficiency in RTL (Verilog/SystemVerilog), functional verification, synthesis/static timing, low-power techniques; exposure to SPI/I2C/UART; scripting (Python, Tcl, Perl).
Verilog, SystemVerilog, Synopsys Design Compiler, Cadence Genus, Python, Tcl, Perl
2mo
Save
Mark Applied
Hide
Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
3mo
Save
Mark Applied
Hide
Staff Wireless IC Digital Designer
Dallas, Texas, United States
OnsiteFull Time
8+ YOESenior level design engineer with 8-12 years in digital RF/wireless design, IC/SoC development, RTL, and verification.
RTL, Synthesis, STA, ATPG, RFIC, SoC, Digital design, FPGA design
2d
Save
Mark Applied
Hide
FPGA Designer
Dallas, Texas, United States
HybridFull Time
5+ YOERequires 5+ years designing FPGA systems with RTL, Verilog, or VHDL; experience with Xilinx or Altera devices and tools, simulations, verification, and timing closure; strong English communication; and a relevant bachelor's degree.
FPGA, CPLD, Xilinx, Intel, Altera, RTL, Verilog, VHDL, SystemVerilog, Xilinx Vivado, Altera Quartus, ModelSim, DSP, AI