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SR RTL DESIGN
Boise, Idaho, United States
HybridFull Time
4+ YOEMaster’s or Bachelor’s in Electrical Engineering with 4+ or 5+ years pre-silicon RTL/ASIC design; Verilog/SystemVerilog; UPF; CDC/RDC; Synthesis and STA; RTL-to-GDS flows.
Verilog, SystemVerilog, UPF, CDC, RDC, Synthesis, STA
1mo
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SR RTL DESIGN
Boise, Idaho, United States
OnsiteFull Time
4+ YOEMaster's in EE +4 yrs or Bachelor's in EE +5 yrs; proficiency in Verilog/SystemVerilog, RTL design and low-power methodologies (UPF, CDC/RDC), synthesis, STA, and RTL simulation; strong collaboration and PPA focus.
Verilog, SystemVerilog, UPF, CDC, RDC, RTL-to-GDS, lint, synthesis, logic synthesis, RTL simulation tools, static timing analysis
1mo
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Principal RTL Design
Boise, Idaho, United States
OnsiteFull Time
8+ YOEMaster's EE with 8+ years or Bachelor's EE with 10+ years RTL/pre-silicon design; ownership of complex RTL/IP, low-power ASIC methodologies (UPF), Verilog/SystemVerilog, STA, synthesis, CDC/RDC experience.
Verilog, SystemVerilog, UPF, CDC, RDC, STA, lint, synthesis
3mo
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PRINICPAL RTL DESIGN
Boise, Idaho, United States
HybridFull Time
8+ YOELead RTL design of DRAM IP; requires advanced degree with 8+ years or 10+ years pre-silicon RTL experience; strong Verilog/SystemVerilog; low-power design; RTL signoff.
Verilog, SystemVerilog, UPF, CDC, RDC, Synthesis, Static Timing Analysis, Verification Tools
2mo
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Semiconductor Product Engineer
Boise, Idaho, United States
HybridFull Time
Master’s degree in Computer or Electrical Engineering or related field; strong knowledge of memory interfaces/protocols; system-level characterization; RTL (VHDL/Verilog/SystemVerilog); DFT; experience with diagnostic tools; ability to run experiments and present data; occasional telecommuting.
DDR, HBM, LPDDR, GDDR, CXL, UCIe, PCIe, Oscilloscopes, Logic Analyzers, Signal Generators, Multimeters, RTL, VHDL, Verilog, SystemVerilog, DFT
2mo
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Principal Circuit Design Engineer - DRAM Design
Boise, Idaho, United States
HybridFull Time
6+ YOEBachelor's in EE or equivalent, 6+ years digital/RTL circuit design, experience with RTL, STA, timing closure, power delivery network design, proficiency with UNIX and Cadence; master's and synthesis/IC compiler experience preferred.
RTL, STA, UNIX, Cadence, synthesis tools, IC compilers
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Principal Circuit Design Engineer - DRAM Design
Boise, Idaho, United States
OnsiteFull Time
6+ YOEBachelor’s in Electrical Engineering; 6+ years in digital/RTL circuit design; UNIX and Cadence experience; RTL design, STA, timing closure; power delivery network design.
UNIX, Cadence, RTL design tools
3mo
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New College Grad - Design and Verification Engineer, Pathfinding
Folsom or Boise or San Jose
$67k-$142k/yr OnsiteFull Time
Bachelor’s, Master’s, or Ph.D. in Electrical Engineering or Electronics; UNIX and Cadence; circuit- and memory-verification experience; DFT and RTL/STA knowledge preferred.
UNIX, Cadence, SystemVerilog, Verilog, SPICE, Schematic entry
2mo
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Semiconductor Product Engineer
Boise, Idaho, United States
HybridFull Time
Expertise with memory interfaces (DDR, HBM, LPDDR, GDDR, CXL, UCIe, PCIe), system-level characterization using oscilloscopes/logic analyzers, RTL (VHDL, Verilog, SystemVerilog), DFT, 8D failure documentation, and customer integration support; Master's in relevant engineering fields accepted.
Oscilloscope, Logic Analyzer, Signal Generator, Multimeter, Thermal Chamber, VHDL, Verilog, SystemVerilog
3d
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Senior Silicon Engineer
Redmond or Mountain View or Santa Clara or Austin or Raleigh or Hillsboro or Boise
$120k-$235k/yr HybridFull Time
5+ YOEExperience verifying silicon using UVM/C, strong RTL and SoC verification background, proficiency with Verilog/System Verilog, and relevant EE/CS/CE degree or equivalent experience.
UVM, C, Verilog, System Verilog, Microsoft Excel
2mo
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
2mo
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FPGA Engineer (Idaho, Boise)
Boise, Idaho, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
RTL, C/C++, Python, VHDL, Verilog, Tcl; hardware security; Xilinx; Vivado; IP core development; system integration; cryptography; hardware/software co-design; experience with simulation and verification tools; ability to obtain/maintain U.S. government security clearance.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, AXI, Avalon, ACE, IP core design, HDL
3mo
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Design and Verification Engineer, Pathfinding
Folsom or Boise or San Jose
$67k-$170k/yr OnsiteFull Time
Degree in electrical engineering or related field; proficiency with UNIX and Cadence environments; experience with SystemVerilog/Verilog, SPICE, SPF, and circuit-level verification; knowledge of semiconductor physics; full-chip functional verification experience.
UNIX, Cadence, SPICE, SystemVerilog, Verilog, SPF, DFT, RTL, STA
2mo
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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
2d
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Senior Principal ASIC FPGA Engineer
Boise or United States
$191k-$212k/yr HybridFull Time
10+ YOEBachelor's (or Master's) in ECE or related plus 8–10+ years ASIC/FPGA experience, DoD Secret clearance, RTL and timing-closure expertise, FinFET and foundry flow experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
1d
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Staff Verification Design Engineer, DRAM
Boise, Idaho, United States
OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years verification experience,strong DRAM/memory architecture knowledge,proficiency with HSPICE and Python,and experience in circuit/system verification.
HSPICE, Python, Verilog, SPICE, STA, RTL
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