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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
1mo
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Senior DFT Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
7+ YOEB.S./M.S. in EE or related, 7+ years DFT experience for complex SoCs, RTL DFT insertion, ATPG and pattern generation, MBIST/LBIST, scan architectures, low-power DFT, mixed-signal test methods, and strong RTL/gate/silicon debugging.
ATPG, MBIST, LBIST, RTL, IEEE 1149.x (JTAG)
2mo
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SLD FPGA Verification Engineer III - Lunar Permanence
Seattle or Space Coast
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBS/MS in Electrical or Computer Engineering; 5+ years FPGA/ASIC verification; RTL simulation tools; UVM; testbench development; DO-254 knowledge a plus.
QuestaSim, ModelSim, SystemVerilog, UVM, RTL, DO-254
3mo
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FPGA Engineer (WA, Seattle)
Seattle, Washington, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Designing and maintaining FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog, Vivado; surveillance clearance eligibility; travel up to 10%.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, cocotb, pyuvm
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
1mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
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Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
3w
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SLD Avionics FPGA Engineer III - Lunar Permanence
Seattle or Denver
$120k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBachelor's/Master's in engineering or related field,5+ years FPGA/ASIC design and verification,RTL in Verilog/SystemVerilog/VHDL,FPGA tools and simulators,UVM/OVM testbenches,ability to travel ~10%,U.S. work authorization required.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Lattice Diamond, Radiant, Microchip Libero, ModelSim, QuestaSim, Perl, Python, Tcl, Git, SVN, AMBA, AXI, AHB, APB, IEEE 802.3, XAUI, JESD204, I2C, SPI, UVM, OVM
15h
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Senior ASIC Emulation Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python,Perl,TCL), firmware and C/C++ integration, pre/post-silicon debug.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C/C++, HAPS, Protium, APB, AHB, AXI, JTAG, SPI, PCIe, Ethernet, USB
1mo
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Senior FPGA Engineer
Seattle, Washington, United States
$120k-$225k/yr OnsiteFull Time
3+ YOE3+ years FPGA design experience with VHDL or SystemVerilog; bachelor's in CS/CE/EE/math or 3+ years professional software experience; experience with complex digital, mixed-signal, or RF FPGA systems.
VHDL, SystemVerilog, RTL, Rust, C++, C, Python, Xilinx SoC, Ethernet, PCIe, JESD204C, AXI, AXI-Stream, TCL, Bash, Linux, Hardware In The Loop, Software In The Loop
1mo
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ASIC Engineering Technical Leader - CDC
San Jose or Austin or Seattle
$184k-$264k/yr HybridFull Time
8+ YOEExpertise in RTL development, CDC/RDC methodology, and static glitch analysis; 6–8+ years related experience (varies by degree); experience maintaining CDC/RDC flows and signing off constraints and waivers.
RTL, SDC, VCS, SystemVerilog Assertions (SVA)
1mo
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Principal ASIC Design Verification Engineer
Seattle, Washington, United States
$190k-$285k/yr OnsiteFull Time
10+ YOEB.S. or M.S. in EE/CE or related, 10+ years ASIC/SoC verification, SystemVerilog/UVM/SVA, simulation and waveform tools, scripting (Python/Perl/TCL), Git and CI/CD, RTL/DFT knowledge, experience with APB/AHB/AXI.
SystemVerilog, UVM, SVA, VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, CI/CD, C, C++, APB, AHB, AXI
1mo
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Senior ASIC Design Verification Engineer - Terawave
Texas or Seattle or Los Angeles or California
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, assertions, coverage closure, RTL/testbench debugging, cross-functional collaboration; must meet U.S. employment eligibility.
System Verilog, UVM
1mo
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Principal ASIC Physical Design Engineer
Seattle, Washington, United States
$190k-$280k/yr OnsiteFull Time
10+ YOEBachelor's or Master's in EE/CE, 10+ years ASIC physical design experience with RTL-to-GDSII flows, Synopsys/Cadence/Siemens tool expertise, timing closure, IR drop and ECO experience, FinFET process knowledge, vendor management, technical leadership, and U.S. person or export-license eligibility.
Synopsys, Cadence, Siemens, TSMC, GDSII, UPF/CPF
1d
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$144k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEBS in EE/CE,7+ years digital design and SoC/FPGA experience,proficiency in SystemVerilog/Verilog,experience with SoC integration,timing knowledge,and simulation/debugging skills.
SystemVerilog, Verilog, Questasim, AXI, AHB, FPGA, SoC, RTL
1mo
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Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
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