2mo
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PHY RTL Design Engineer
Los Angeles or San Diego or San Francisco
OnsiteFull Time
Bachelor's in related field; DSP fundamentals; digital communications; RTL design experience; strong communication skills.
MATLAB, RTL Design, UVM, DV, FPGA, Emulation, Synthesis, Power Analysis, EDA Tools
1mo
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
1mo
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Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$125k-$195k/yr HybridFull Time
6+ YOEBachelor's in EE/CS (required). 6+ years FPGA design (or 4+ with MS, 2+ with PhD). Experience with fixed‑point DSP, multi‑clock FPGA designs, Xilinx FPGAs and Vivado. U.S. Person required; background check and drug test required.
Xilinx FPGAs, Vivado IDE, MATLAB, logic analyzers
2mo
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DDR Design Engineer
Los Angeles or Irvine
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with RTL design, Verilog/SystemVerilog, DFT, timing, power, and DDR PHY design.
Verilog, SystemVerilog, DFT, RTL design, Timing constraints, Formal verification, Equivalence checking, Unified Power Format
1mo
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FPGA Design Engineer
Los Angeles or Irvine
$100k-$140k/yr HybridFull Time
6+ YOESenior FPGA design expert with 6+ years (MS: 4y; PhD: 2y) in fixed-point DSP, multiple clock-domain FPGA designs, Xilinx Vivado.
Xilinx FPGA, Vivado, MATLAB, HDL, FPGA design, RTL coding
3mo
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Sr. ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering or computer science; 5+ years RTL/FPGA/ASIC experience.
Verilog, SystemVerilog, RTL, FPGA, ASIC, Python, TCL, EDA tools (HDL simulators: VCS, Questa, IES), Spyglass, Xilinx Vivado, Quartus II, AXI, AHB
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
1mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
1mo
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Sr. FPGA Engineer
El Segundo or Los Angeles or Hawthorne
$160k-$225k/yr OnsiteFull Time
5+ YOEB.S. in engineering or CS, 5+ years FPGA/RTL experience, Verilog/SystemVerilog, Vivado toolchain, AXI protocols, ARM/SoC FPGA experience, Python/Bash scripting, U.S. Person status required.
Verilog, SystemVerilog, ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream), Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP/UDP/IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins, NTP, PTP, Ettus, NI, HackRF, HLS Synthesis, GPU
1mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
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Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
1mo
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Senior FPGA Engineer
Hawthorne or El Segundo or Los Angeles
$160k-$250k/yr OnsiteFull Time
8+ YOEBachelor’s in CE/EE/CS, 8+ years FPGA development with SystemVerilog or VHDL, familiarity with Xilinx Vivado/Vitis, experience with high-speed I/O and board bring-up, strong timing and RTL skills.
SystemVerilog, VHDL, Xilinx Vivado, Vitis, Xilinx Zynq Ultrascale+ MPSoC, C/C++, embedded Linux
3mo
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Principal ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$200k-$285k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE/CS; 8+ years RTL/FPGA/ASIC; Verilog/SystemVerilog; experience with ASICs/FPGA; scripting (Python, TCL).
Verilog, SystemVerilog, VCS, Questa, IES, Spyglass, Xilinx Vivado, Altera Quartus II, Python, TCL
1mo
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Senior ASIC Design Verification Engineer - Terawave
Texas or Seattle or Los Angeles or California
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, assertions, coverage closure, RTL/testbench debugging, cross-functional collaboration; must meet U.S. employment eligibility.
System Verilog, UVM