3mo
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RTL Design Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with RTL design and Verilog/SystemVerilog preferred.
Verilog, SystemVerilog, Python, Perl
3mo
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RTL Design Engineer
Austin or Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 2+ years experience; knowledge of RTL design, Verilog/SystemVerilog, and basic digital design.
Verilog, SystemVerilog, VHDL, Design Compiler, Genus, Python, Perl, TCL, ModelSim, VCS, Xcelium, UVM, OVM
2mo
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Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
3mo
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Principal Digital Design Engineer
Chandler or Vancouver or Remote
$200k-$250k/yr HybridFull Time
10+ YOEBachelor's or master's in electrical/computer engineering; 10+ years in digital design with RTL; SoC/subsystem tapeout experience; strong RTL, microarchitecture, back-end flows, DFT/scan, LEC, STA, SDC skills; solid timing, power, and debug expertise.
Synopsys, Cadence, EDA tools, Synthesis, DFT, LEC, STA, SDC, UPF/CPF, RTL
2mo
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Senior Engineer, Digital Design Engineering
Beaverton, Oregon, United States
$122k-$174k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2 years of digital design/verification experience; proficiency with RTL, Verilog/SystemVerilog, and CAD tools; knowledge of verification methods and test benches.
Verilog, SystemVerilog, Cadence, Synopsys, RTL design, Test benches, ASIC design flow
1d
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
5+ YOEExperience in SOC physical design, low-power methodology, RTL-to-GDS implementation, signoff (timing, physical verification, EMIR, formal equivalence), and collaboration across CAD, RTL, architecture, and power teams.
PrimePower
2w
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$136k-$265k/yr OnsiteFull Time
5+ YOEMasters in Computer or Electrical Engineering or equivalent,5+ years chip/SOC design experience,RTL/verification and design automation expertise,proficient in scripting (Perl/Python),strong analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
23h
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with 8+ years ASIC/SoC design experience; RTL-to-silicon expertise, Synopsys/Cadence tool experience, Verilog/SV and scripting languages, strong communication and problem-solving skills.
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
1w
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MTS Logic Design
Hillsboro, Oregon, United States
$86k-$160k/yr HybridFull Time
Bachelor's degree in engineering, knowledge of Verilog/System Verilog, RTL design and verification, strong communication skills.
Verilog, System Verilog, RTL
23h
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,experience with Synopsys and Cadence tools,proficiency in Verilog,SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
2w
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOEMasters in Computer/Electrical Engineering or equivalent experience,5+ years chip/SOC design experience,RTL (Verilog),UVM/System Verilog,design automation,Perl/Python skills,analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
23h
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with VLSI focus,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,knowledge of Synopsys and Cadence flows,proficiency in Verilog/SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, Subversion, git, GitHub, FPGA, AI Copilot (LLM-based tools)
2w
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Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin or San Jose
$123k-$197k/yr OnsiteFull Time
3+ YOEBachelor's (5+ yrs) or Master's (3+ yrs) in EE or related, experience with FPGA RTL, timing closure, simulation, DRAM/Flash interfaces, Verilog, C/C++, and lab validation.
Verilog HDL, C, C++, Altera/AMD FPGA tool flows, UVM, Linux, Windows
2w
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Senior CPU Performance Architect
Austin or Portland or Mountain View or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.
ARM, RISC-V, x86, RTL, Linux
4w
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Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
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