5d
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FPGA Development Engineer, Bespoke Solutions
Jessup or Arlington or Herndon
$110k-$160k/yr OnsiteFull Time
3+ YOEBachelor's in electrical/related field,3+ years developing programmable logic (VHDL/System Verilog/Verilog),current US Top Secret/SCI clearance required,EMBedded/RTL debug and performance tradeoff experience.
VHDL, System Verilog, Verilog, RTL, Xilinx Ultrascale+ FPGAs, Versal ACAPs, Intel Agilex SOCs
1mo
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Digital Design Engineer - Level 5 - Linthicum
Linthicum, Maryland, United States
$186k-$279k/yr OnsiteFull Time
7+ YOEDegree in EE/CE/CS (Bachelor’s+12yr or Master’s+10yr or PhD+7yr), FPGA/ASIC/HDL (Verilog, VHDL) experience, FPGA IDEs (Xilinx, Microsemi), test/verification and RTL debug, mentoring skills, U.S. citizenship and ability to obtain Top Secret clearance.
Xilinx, Microsemi, HDL, Verilog, VHDL, RTL
1w
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Lead ASIC Digital Design Engineer
Annapolis Junction or Telework or Boise or Salt Lake City or Bloomington
$177k-$187k/yr RemoteFull Time
8+ YOE8+ years ASIC/FPGA RTL design experience, ASIC tape-out and timing-closure experience, familiarity with FinFET nodes and commercial foundry flows, EDA tool and JIRA proficiency, strong RTL and microarchitecture skills.
JIRA, Microsoft Office
1w
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (Master's+3 acceptable), U.S. citizenship, ability to obtain DoD Secret clearance, 5–8+ years ASIC/FPGA RTL design experience, formal verification and verification-process experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office, STA
1w
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in ECE or related and 5+ years experience (or Master's+3); US citizenship and ability to obtain DoD Secret clearance; strong RTL/ASIC design and verification experience.
JIRA, Microsoft Office
1w
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FPGA Verification Engineer Level 3/4 - Linthicum
Linthicum, Maryland, United States
$120k-$179k/yr OnsiteFull Time
3+ YOEU.S. citizen required. FPGA verification experience with VUnit, HDL (SystemVerilog/Verilog/VHDL), testbench and coverage-driven verification, RTL debug, test plan development; ability to obtain DoD Secret/Top-Secret clearance.
VUnit, SystemVerilog, Verilog, VHDL, Synopsys, Mentor Graphics, SystemVerilog Assertions (SVA), Bash, Perl, Python, Tcl, Makefile, Xilinx, MicroChip, Kintex, Zynq ultrascale+, RTG4
6d
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Lead ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$177k-$187k/yr RemoteFull Time
8+ YOEBachelor's in ECE or related plus 8+ years (or Master's plus 6+ years), strong RTL/ASIC/FPGA design experience, ASIC tape-out and timing closure experience, ability to obtain DoD Secret clearance, proficiency with JIRA and Microsoft Office.
JIRA, Microsoft Office
23h
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE,10+ years FPGA design experience with Xilinx Vivado, Verilog/VHDL, RFSoC/Versal platforms, RTL-to-hardware validation, AXI interfaces, and eligibility for DoD Secret clearance.
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Versal, Versal ACAP, ADRV9009, AD9081, ADRV9009-ZU11EG, AXI-Lite, AXI-Stream, JESD204B, JESD204C, JTAG, Integrated Logic Analyzer (ILA), VIO, Ethernet, PCIe, Tcl, Python
1mo
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA design experience, strong Verilog/VHDL and Xilinx Vivado skills, RFSoC/Versal experience, RTL simulation and hardware debug experience, U.S. citizenship and Secret clearance (or ability to obtain).
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Integrated Logic Analyzer (ILA), VIO, JTAG, ADRV9009, AD9081, JESD204B/C, Ethernet, PCIe, Aurora, AXI-Lite, AXI-Stream, DMA, Tcl, Python
1w
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Engineering and Physical Sciences Researcher- Mid to Experienced Level (Maryland)
Fort Meade, Maryland, United States
$105k-$193k/yr OnsiteFull Time
3+ YOEDegree in engineering, physics/astronomy, or related technical field; relevant research or engineering experience; publication and collaboration record; demonstrated technical skills in device/ASIC/architecture research.
Verilog, RTL, FPGA, Cadence, Synopsys