3mo
Save
Mark Applied
Hide
RTL Design Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design experience; Verilog/SystemVerilog; front-end tools; mixed-signal and analog concepts; scripting (Perl, JSON, Python); GenAI tooling for RTL design.
Verilog, SystemVerilog, Verilog simulators, UPF, Python, Perl, JSON
3w
Save
Mark Applied
Hide
Interconnect Micro-architect/RTL Design Engineer
Austin or Boxborough
$156k-$268k/yr HybridFull Time
Experienced RTL design engineer with strong Verilog/System Verilog skills, knowledge of C/C++ and scripting (Perl or Python), digital/high-speed design understanding, and experience with multi-processor coherency, DFT-friendly RTL and post-silicon debug.
Verilog, System Verilog, C, C++, Perl, Python, x86, ARM
3mo
Save
Mark Applied
Hide
Senior Staff RTL Design Engineer- 16908
Boxborough, Massachusetts, United States
$138k-$208k/yr OnsiteFull Time
10+ YOE10+ years ASIC digital design experience with production RTL ownership, Verilog and Perl proficiency, knowledge of synthesis, timing analysis, and power optimization; Bachelor's degree in EE/CE or related field required.
Verilog, Perl
2mo
Save
Mark Applied
Hide
RTL Design Engineer (North Reading, MA, US)
North Reading, Massachusetts, United States
$123k-$197k/yr OnsiteFull Time
5+ YOEBSEE or MSEE with 5+ years; extensive RTL Verilog; CDC/STA; memory/serial interfaces; scripting (Python, Tcl, Make).
Verilog, Python, Tcl, Make
2mo
Save
Mark Applied
Hide
Senior Engineer, Digital Design Engineering
Wilmington, Massachusetts, United States
$124k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital/mixed-signal design and verification; proficiency with RTL, Verilog/SystemVerilog; experience with Cadence or Synopsys tools.
Verilog, SystemVerilog, RTL, Cadence, Synopsys
1w
Save
Mark Applied
Hide
Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$206k-$251k/yr OnsiteFull Time
Expertise in interconnect, cache/coherency and RTL generator design; strong software engineering and hardware RTL skills; BS/MS in EE/CE/CS or equivalent experience.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Bluespec, Git, Github, Jira, Confluence, TileLink, RISC-V, AXI, AHB, APB, CHI
1mo
Save
Mark Applied
Hide
FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
RTL proficiency (Verilog or VHDL), real industry FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD, Lattice, Intel/Altera), embedded C/C++ experience, and experience with prototype bring-up and ASIC verification workflows.
Verilog, VHDL, C, C++, RTL, FPGA, Xilinx, AMD, Lattice, Intel/Altera, ASIC, ADC, DAC
1mo
Save
Mark Applied
Hide
Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
2mo
Save
Mark Applied
Hide
FPGA Engineer (MA, Boston)
Boston, Massachusetts, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, HDL, C/C++, Python; VHDL/Verilog; hardware security; IP core development; FPGA toolchains; Xilinx/Intel devices; simulation and verification; system integration; embedded software testing; cryptography; cocotb/pyuvm.
RTL, VHDL, Verilog, Python, C, C++, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, Xilinx, FPGA verification tools, cocotb, pyuvm
1mo
Save
Mark Applied
Hide
Staff Engineer, Design Verification
Westborough, Massachusetts, United States
$128k-$189k/yr OnsiteFull Time
2+ YOEBachelor's/Master's/PhD in CS/EE or related; 2–5 years verification experience; strong UVM, constrained-random, coverage, SVA, RTL simulation, C/C++, Python/Perl, and Linux skills.
UVM, SVA, RTL, C/C++, Python, Perl, Linux, AMBA, PCIe, Ethernet
2mo
Save
Mark Applied
Hide
Principal Firmware/FPGA Engineer (Onsite)
Cambridge, Massachusetts, United States
$108k-$205k/yr OnsiteFull Time
8+ YOE8+ years in STEM or an advanced degree with 5+ years; FPGA RTL/Verilog/VHDL; DSP fundamentals; high-speed interfaces; scripting; ability to obtain security clearance
Verilog, VHDL, RTL, FPGA, C++, Python, bash, Tcl, Ethernet, sFPDP, HBM2, DDR, Linux, Petalinux
2mo
Save
Mark Applied
Hide
Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
1mo
Save
Mark Applied
Hide
Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
1mo
Save
Mark Applied
Hide
Sr. FPGA Engineer
Marlborough, Massachusetts, United States
OnsiteFull Time
5+ YOEBachelor's in Engineering required (Master's preferred), 5+ years FPGA RTL experience with Verilog/SystemVerilog, 3+ years software development (C/C++/C#/Python), experience with QuestaSim, Vivado, Quartus, Git/CI-CD, ARM/Linux integration; MATLAB/DSP desirable.
Verilog, SystemVerilog, C, C++, C#, Python, QuestaSim, Vivado, Quartus, MATLAB, ARM, Linux, Git, CI/CD
1mo
Save
Mark Applied
Hide
Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
6d
Save
Mark Applied
Hide
Mixed Signal Logic Design Engineer
Hillsboro or Santa Clara or Austin or Massachusetts
$164k-$232k/yr HybridFull Time
4+ YOEExpert-level Verilog/SystemVerilog RTL design, digital logic and RTL-to-GDSII flow knowledge; 4+ years industry experience (Master's) or 7+ years (Bachelor's); mixed-signal integration and debugging skills.
Verilog, SystemVerilog, EDA tools, Perl, TCL/Tk, Python, STA
2w
Save
Mark Applied
Hide
Senior Engineer (Andover, MA)
Andover, Massachusetts, United States
$101k-$111k/yr HybridFull Time
Bachelor's in CS/CE or related; experience/coursework in digital/electronics design and verification, MATLAB/Python, SPICE/Simetrix/SIMPLIS/NL5, Verilog/SystemVerilog, UVM, RTL simulators, FPGA emulation, ARM/C, scripting (Perl/Tcl/Python), STA and UPF constraints.
Matlab, Python, Spice, Simetrix, SIMPLIS, NL5, Verilog, SystemVerilog, Xcelium, ModelSim, NCsim, UVM, FPGA emulators, ARM, C, Perl, Tcl, Unix, Linux, STA, UPF
1mo
Save
Mark Applied
Hide
Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
1mo
Save
Mark Applied
Hide
Senior LPU ASIC Engineer
Santa Clara or California or North Carolina or Oregon or Arizona or Massachusetts or United States
$136k-$265k/yr HybridFull Time
5+ YOEB.S. in ECE or equivalent with 5+ years delivering full‑flow physical design for large SoCs; expertise in RTL-to-GDSII flow, low-power (UPF), timing/CTS, PPA optimization, sign-off integrity, DFT, and scripting (TCL/Python/Perl).
TCL, Python, Perl
2w
Save
Mark Applied
Hide
Senior ASIC Hardware Design Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors in EE/CE/CS (or equivalent) and 5+ years experience; strong Verilog/SystemVerilog skills, RTL/micro-architecture experience, Python/Perl scripting, understanding of physical implementation and VLSI.
Verilog, SystemVerilog, Perl, Python
Explore Jobs
Expand Your Job Search
Top Cities in Massachusetts for Rtl Engineer
- Rtl Engineer jobs in Boston, MA
- Rtl Engineer jobs in Worcester, MA
- Rtl Engineer jobs in Springfield, MA
- Rtl Engineer jobs in Lowell, MA
- Rtl Engineer jobs in Cambridge, MA
- Rtl Engineer jobs in New Bedford, MA
- Rtl Engineer jobs in Brockton, MA
- Rtl Engineer jobs in Fall River, MA
- Rtl Engineer jobs in Quincy, MA
- Rtl Engineer jobs in Lynn, MA
- Rtl Engineer jobs in Newton, MA
- Rtl Engineer jobs in Somerville, MA
- Rtl Engineer jobs in Lawrence, MA
- Rtl Engineer jobs in Framingham, MA
- Rtl Engineer jobs in Waltham, MA
- Rtl Engineer jobs in Haverhill, MA
- Rtl Engineer jobs in Malden, MA
- Rtl Engineer jobs in Brookline, MA
- Rtl Engineer jobs in Medford, MA
- Rtl Engineer jobs in Taunton, MA