1mo
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SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)
Richardson or Folsom
$177k-$334k/yr OnsiteFull Time
15+ YOEBachelors or Masters in electrical/computer engineering; 15+ years in related field; SystemVerilog/Verilog; RTL-to-GDS flow; Cadence/Synopsys/Siemens; Python/TCL/Perl.
SystemVerilog, Verilog, RTL, EDA tools (Cadence, Synopsys, Siemens), Python, TCL, Perl
2mo
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Lead ASIC/FPGA Design Engineer
Livermore, California, United States
OnsiteFull Time
5+ YOELead RTL design of high-speed ASIC/FPGA modem; strong DSP, FEC integration, and power/performance optimizations; requires security clearance.
Verilog, SystemVerilog, LINT, CDC, RDC, Test benche s, Synthesis, Power/Area analysis, STA, Place and Route
1mo
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Senior Engineer Space Electronics
Pleasanton, California, United States
$142k-$186k/yr OnsiteFull Time
3+ YOEBachelor's in EE (or related) with 6+ yrs or Master's with 3+ yrs; 3+ yrs space/LEO electronics design; experience with power, analog, mixed‑signal, radiation testing/mitigation; LTSpice proficiency; high‑speed PCB design and lab test equipment experience; must be U.S. Person.
LTSpice, FPGA, MCU, RTL, AS9100, Oscilloscope, VNA, Spectrum Analyzer, Power Supply, Function Generator, DVM