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FPGA Engineer - Control Systems
Princeton, New Jersey, United States
$150k-$235k/yr OnsiteFull Time
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
RTL, FPGAs, ASICs, Xilinx, AMD, RFSoC
2w
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DSP Engineer
New York or New Jersey or United States
RemoteFull Time, Contract
7+ YOEMS in Electrical Engineering (DSP focus) required; 7+ years FPGA design with synthesizable RTL, VHDL/Verilog/SystemVerilog, Vivado/Vitis toolchains, high-speed serial interfaces (JESD204B/C, PCIe, Ethernet), SOC/FPGA platforms, and strong lab debugging skills.
Vivado, Vitis, VHDL, Verilog, SystemVerilog, JESD204B, JESD204C, PCIe Gen3, PCIe Gen4, Ethernet, Aurora, AMD RFSoC, Zynq Ultrascale+, Versal AI Core, Microchip PolarFire, AXI
3w
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Customer Projects Hardware Engineer – Aerospace, Defense & Government (ADG)
Hazlet or Portsmouth
$135k-$195k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CE or related, 6+ years hardware design/RTL/board-level experience, FPGA systems familiarity, high-speed interface knowledge (DDR, PCIe, Ethernet), lab debugging experience, eligible for U.S. security clearance.
oscilloscope, logic analyzer, RTL, PCIe, Ethernet, DDR
2w
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FPGA Engineer
New York or New Jersey or United States
RemoteFull Time
5+ YOE5–7 years FPGA/ASIC experience, DSP proficiency, RTL (VHDL/Verilog/SystemVerilog), FPGA toolchains, high-speed interfaces, MATLAB/Simulink or Python, and SoC/embedded integration experience.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Vitis, Intel Quartus, JESD204, LVDS, SERDES, MATLAB, Simulink, Python, RFSoC, Xilinx/AMD Versal, Zynq, Git, eCPRI, Ethernet
1mo
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Senior Engineer, Digital Design Engineering
Somerset, New Jersey, United States
$127k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital design/mixed-signal verification; experience with RTL, Verilog/SystemVerilog, and ASIC/FPGA design flows.
Verilog, SystemVerilog, Cadence, Synthesis, CDC, Verifications tools
2mo
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FPGA Engineer (NJ, Moorestown)
Moorestown, New Jersey, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Familiar with RTL, C/C++, Python, VHDL/Verilog, hardware security, FPGA design, and hardware-software integration; eligible for U.S. government security clearance; willingness to travel ~10%.
VHDL, Verilog, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm, Python, C, C++, Tcl
1mo
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Principal Digital Design Engineer (ASIC)
Somerset or Wilmington
$160k-$239k/yr OnsiteFull Time
10+ YOE10+ years ASIC/SoC digital design experience, Bachelor’s degree in EE/CE, expertise in SystemVerilog/Verilog, RTL design, synthesis, timing closure, MATLAB/TCL/Python modeling, Cadence tools, and tapeout experience.
SystemVerilog, MATLAB, Verilog, Python, TCL, Cadence, UVM