14 rtl engineer jobs at 9 companies in Norwalk, CT
1mo
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
4d
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Hardware Engineer, RTL/PD
New York City or London or Zurich or Palo Alto or Copenhagen or Seoul
$200k-$285k/yr OnsiteFull Time
Production SystemVerilog RTL experience, synthesis and place-and-route through tapeout, experience with backend flows and timing closure, familiarity with formal methods and post-silicon bring-up; multiple tapeouts preferred.
SystemVerilog, RISC-V, GDSII, CTS, DFT, LVS, DRC
1mo
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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
1mo
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Senior FPGA Engineer
Chicago or New York City or London or United States or Canada or Europe or Asia
OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering, 3+ years FPGA/hardware experience, Verilog/System Verilog and RTL skills, FPGA design flow (synthesis, place & route, static timing), SoC and TCP/IP knowledge, lab debugging, EM/board characterization.
Verilog, System Verilog, RTL, TCP/IP, XILINX, ALTERA
2mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
22h
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
2w
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
1mo
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FPGA Design Engineer
New York City, New York, United States
$200k-$280k/yr OnsiteFull Time
Proven FPGA experience bringing RTL to timing-closed hardware; expert SystemVerilog/VHDL and Xilinx Vivado; PCIe and common bus protocols; strong Python/C++ for automation; board bring-up and lab debugging skills.
SystemVerilog, VHDL, Xilinx Vivado, ILA, Vivado Analyzer, Python, C++, PCIe, AXI, AHB, SPI, UART, JTAG, HAPS, VCU118, VPK180, Cocotb, UVM, OSVVM, hls4ml, FINN, GitLab CI, Docker, oscilloscope, logic analyzer
22h
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ASIC Physical Design Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
8+ YOE8+ years building and running physical design flows; ability to own PD flow end-to-end, read and write RTL, and use high-level programming to improve hardware tools.
Hardcaml, OCaml, Python, C++, Haskell
3w
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
1w
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Senior Digital ASIC Design Engineer
Upton, New York, United States
$115k-$145k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE/applied physics, 7+ years digital ASIC design, SystemVerilog/Verilog RTL, CAD/EDA tool experience, strong timing/CDC/low-power knowledge, and collaboration with mixed-signal, verification, and firmware teams.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, Tcl, Python, Perl, Make, shell
1w
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Sr Frontend Engineer (1 year Contract)
New York, New York, United States
$179k-$203k/yr HybridContract
5+ YOE5+ years frontend experience with React 18 and TypeScript 5, GraphQL integration, TanStack Query/Apollo, React Router 6, Vite/SWC, Tailwind/MUI/Radix, testing (RTL, Playwright), accessibility, and frontend performance.
React 18, TypeScript 5, Vite, SWC, esbuild, GraphQL, GraphQL Code Generator, TanStack Query, Apollo Client, React Router 6, Tailwind CSS, Material UI 7, Radix UI, shadcn/ui, AG Grid, Recharts, React Testing Library, Playwright, Next.js, Remix, Framer Motion, Storybook, SWR
3w
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Senior CPU Performance Architect
Austin or Portland or Mountain View or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.
ARM, RISC-V, x86, RTL, Linux