22 rtl engineer jobs at 7 companies in Olivehurst, CA
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HBM SoC RTL Design Engineer
Folsom, California, United States
$121k-$247k/yr OnsiteFull Time
3+ YOE3+ years SoC/RTL design experience, proficiency in SystemVerilog/Verilog, RTL-to-GDS flow knowledge, familiarity with EDA toolchains, scripting (Python/TCL/Perl/shell), and SoC integration skills.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell, Palladium, Veloce, Zebu
1w
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HBM SoC RTL Design Engineer
Folsom, California, United States
$121k-$247k/yr OnsiteFull Time
3+ YOEBachelor's or master's in EE/Computer Engineering with 3+ years experience, proficiency in SystemVerilog/Verilog, RTL‑to‑GDS flow, EDA tools, and scripting (Python/TCL/Perl/shell).
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, Tcl, Perl, Shell, Palladium, Veloce, Zebu
19h
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Senior Staff Digital Design Power Engineer
Folsom, California, United States
$170k-$246k/yr OnsiteFull Time
6+ YOEMaster's degree in electrical engineering, computer engineering, computer science, or related field, plus six years of related experience and expertise in VLSI development, RTL design, synthesis, and physical design.
VLSI, RTL
3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
1mo
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
6d
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Principal Engineer - Design
Roseville, California, United States
$75k-$232k/yr OnsiteFull Time
10+ YOE10+ years experience in SoC design/verification, BS/MS in Electrical/Computer Engineering, experience with serial protocols (SAS/SATA/NVMe, PCIe), Linux and C/Python scripting, RTL (VHDL/Verilog/System Verilog).
Cadence Palladium, Protium, Linux, C, Python, Tcl, Bash, VHDL, Verilog, System Verilog, JTAG, I2C
3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
2mo
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Mixed Signal Logic Design Engineer
Folsom or San Jose or Santa Clara
$122k-$232k/yr OnsiteFull Time
4+ YOEBachelor's with 4+ years or Master's with 3+ years or PhD with 1+ year in CS/CE/EE; 2+ years RTL design SystemVerilog/Verilog; mixed-signal, UPF, clock gating; VCS/Verdi; FE tools; no visa sponsorship.
SystemVerilog, Verilog, VCS, Verdi, UPF, Lint, CDC, RDC, Synthesis, Voltage Domain Crossings, DDR, LPDDR, VSCode, Git
4d
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GPU Performance Architect
Folsom, California, United States
$106k-$152k/yr HybridFull Time
Undergraduate degree required; preferred background in electrical engineering, computer architecture, or computer science, with experience in GPU performance analysis, AI/ML algorithms, simulation, and programming.
PyTorch, Triton, CUDA, HIP, C, C++, Python, DirectX, Vulkan, PIX, RenderDoc, RTL, AI, ML
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