3mo
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FPGA Engineer (PA, Pittsburgh)
Pittsburgh, Pennsylvania, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, C/C++, Python; VHDL/Verilog; FPGA design, verification, and hardware security concepts; ability to obtain U.S. government security clearance.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Agilex, AXI, ACE, Avalon, IP Core, cocotb, pyuvm
1mo
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Embedded Hardware Engineer
San Jose or Pittsburgh
$160k-$210k/yr OnsiteFull Time
8+ YOE8+ years PCB design and embedded software experience, 5+ years C/C++, experience with silicon bring-up, board bring-up, boot ROM/firmware, RTL/FPGA validation, and embedded platforms (MSP430, STM32, Ambiq Apollo, PIC32).
C, C++, MSP430, STM32, Ambiq Apollo, PIC32, Altium Develop, RTL simulators, FPGA emulators
2mo
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Engineer - FPGA
State College, Pennsylvania, United States
OnsiteFull Time
3+ YOEFPGA design/development, RTL/VHDL/Verilog, Linux experience, and cross-disciplinary collaboration required.
Vivado, Libero, ModelSim, cocotb, Git, C, C++, Python, VHDL, Verilog, SystemVerilog
2mo
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FPGA Engineer
Exton, Pennsylvania, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years FPGA/ASIC in regulated environments; proficient in Verilog/VHDL; Xilinx Vivado; DO-254 familiarity; hardware debugging; cross-functional collaboration
Verilog, VHDL, Xilinx Vivado, RTL simulation, ModelSim/Questa, DO-254 knowledge, I2C, SPI, JTAG, Ethernet, PCIe
2w
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Engineer II-Design
Allentown, Pennsylvania, United States
OnsiteFull Time
2+ YOE2+ years RTL design experience for ASIC, Bachelor’s in EE/CE/CS required, SystemVerilog and scripting (TCL/Perl/Python), Linux, static timing and simulation experience, US citizenship or permanent residency required.
SystemVerilog, Verilog, TCL, Perl, Python, LINUX, FPGA
5d
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Test Engineer
San Jose or Austin or Pittsburgh or Tucson
$150k-$190k/yr OnsiteFull Time
5+ YOE5+ years fabless or IDM semiconductor test experience, hands-on DFT, ATPG/MBIST/JTAG, ATE bringup on Advantest or Teradyne, OSAT coordination, yield analysis, and strong communication skills.
DFT, ATPG, MBIST, JTAG, STIL, PDL, SVF, Advantest, Teradyne, Python, Perl, VCD, RTL
1mo
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Sr. Staff Digital Design Engineer
Pittsburgh, Pennsylvania, United States
$140k-$230k/yr OnsiteFull Time
10+ YOE10+ years experience with digital ASIC/RTL design, Verilog/SystemVerilog, networking protocols (Ethernet, PCIe, CXL, UCIe, UALink), Unix/Linux scripting, Cadence/Mentor/Synopsys tool experience, strong technical leadership and debugging skills.
Verilog, SystemVerilog, Perl, Tcl, Python, Shell, Cadence, Mentor, Synopsys, UVM